313 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ |
314 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ |
314 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ |
315 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ |
315 #define PCI_CHSWP_PI 0x30 /* Programming Interface */ |
316 #define PCI_CHSWP_PI 0x30 /* Programming Interface */ |
316 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ |
317 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ |
317 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ |
318 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ |
|
319 |
|
320 /* PCI Advanced Feature registers */ |
|
321 |
|
322 #define PCI_AF_LENGTH 2 |
|
323 #define PCI_AF_CAP 3 |
|
324 #define PCI_AF_CAP_TP 0x01 |
|
325 #define PCI_AF_CAP_FLR 0x02 |
|
326 #define PCI_AF_CTRL 4 |
|
327 #define PCI_AF_CTRL_FLR 0x01 |
|
328 #define PCI_AF_STATUS 5 |
|
329 #define PCI_AF_STATUS_TP 0x01 |
318 |
330 |
319 /* PCI-X registers */ |
331 /* PCI-X registers */ |
320 |
332 |
321 #define PCI_X_CMD 2 /* Modes & Features */ |
333 #define PCI_X_CMD 2 /* Modes & Features */ |
322 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
334 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
397 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ |
409 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ |
398 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ |
410 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ |
399 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
411 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
400 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
412 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
401 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
413 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
402 #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ |
414 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ |
403 #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ |
415 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ |
404 #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ |
416 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ |
405 #define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ |
417 #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ |
|
418 #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ |
|
419 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ |
|
420 #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */ |
|
421 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
|
422 #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ |
|
423 #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |
406 #define PCI_EXP_LNKCTL 16 /* Link Control */ |
424 #define PCI_EXP_LNKCTL 16 /* Link Control */ |
407 #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ |
425 #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ |
408 #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ |
426 #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
|
427 #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ |
|
428 #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ |
|
429 #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ |
|
430 #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ |
409 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ |
431 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ |
|
432 #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ |
|
433 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ |
|
434 #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ |
410 #define PCI_EXP_LNKSTA 18 /* Link Status */ |
435 #define PCI_EXP_LNKSTA 18 /* Link Status */ |
411 #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ |
436 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
|
437 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ |
|
438 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
412 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
439 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
|
440 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
|
441 #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ |
|
442 #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ |
413 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
443 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
|
444 #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
|
445 #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ |
|
446 #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ |
|
447 #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ |
|
448 #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ |
|
449 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ |
|
450 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ |
|
451 #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ |
|
452 #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ |
|
453 #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ |
|
454 #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ |
|
455 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ |
414 #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
456 #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
|
457 #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ |
|
458 #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ |
|
459 #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ |
|
460 #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ |
|
461 #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ |
|
462 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ |
|
463 #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ |
|
464 #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ |
|
465 #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ |
|
466 #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ |
|
467 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ |
415 #define PCI_EXP_SLTSTA 26 /* Slot Status */ |
468 #define PCI_EXP_SLTSTA 26 /* Slot Status */ |
|
469 #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ |
|
470 #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ |
|
471 #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ |
|
472 #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ |
|
473 #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ |
|
474 #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ |
|
475 #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ |
|
476 #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ |
|
477 #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ |
416 #define PCI_EXP_RTCTL 28 /* Root Control */ |
478 #define PCI_EXP_RTCTL 28 /* Root Control */ |
417 #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ |
479 #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ |
418 #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ |
480 #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ |
419 #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
481 #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
420 #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
482 #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |