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1 /* |
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2 * core.h -- Core driver for NXP PCF50633 |
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3 * |
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4 * (C) 2006-2008 by Openmoko, Inc. |
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5 * All rights reserved. |
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6 * |
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7 * This program is free software; you can redistribute it and/or modify it |
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8 * under the terms of the GNU General Public License as published by the |
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9 * Free Software Foundation; either version 2 of the License, or (at your |
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10 * option) any later version. |
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11 */ |
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12 |
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13 #ifndef __LINUX_MFD_PCF50633_CORE_H |
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14 #define __LINUX_MFD_PCF50633_CORE_H |
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15 |
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16 #include <linux/i2c.h> |
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17 #include <linux/workqueue.h> |
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18 #include <linux/regulator/driver.h> |
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19 #include <linux/regulator/machine.h> |
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20 #include <linux/power_supply.h> |
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21 |
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22 struct pcf50633; |
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23 |
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24 #define PCF50633_NUM_REGULATORS 11 |
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25 |
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26 struct pcf50633_platform_data { |
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27 struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; |
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28 |
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29 char **batteries; |
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30 int num_batteries; |
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31 |
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32 /* Callbacks */ |
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33 void (*probe_done)(struct pcf50633 *); |
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34 void (*mbc_event_callback)(struct pcf50633 *, int); |
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35 void (*regulator_registered)(struct pcf50633 *, int); |
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36 void (*force_shutdown)(struct pcf50633 *); |
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37 |
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38 u8 resumers[5]; |
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39 }; |
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40 |
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41 struct pcf50633_subdev_pdata { |
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42 struct pcf50633 *pcf; |
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43 }; |
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44 |
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45 struct pcf50633_irq { |
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46 void (*handler) (int, void *); |
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47 void *data; |
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48 }; |
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49 |
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50 int pcf50633_register_irq(struct pcf50633 *pcf, int irq, |
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51 void (*handler) (int, void *), void *data); |
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52 int pcf50633_free_irq(struct pcf50633 *pcf, int irq); |
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53 |
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54 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); |
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55 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); |
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56 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); |
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57 |
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58 int pcf50633_read_block(struct pcf50633 *, u8 reg, |
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59 int nr_regs, u8 *data); |
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60 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, |
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61 int nr_regs, u8 *data); |
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62 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); |
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63 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); |
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64 |
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65 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); |
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66 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); |
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67 |
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68 /* Interrupt registers */ |
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69 |
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70 #define PCF50633_REG_INT1 0x02 |
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71 #define PCF50633_REG_INT2 0x03 |
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72 #define PCF50633_REG_INT3 0x04 |
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73 #define PCF50633_REG_INT4 0x05 |
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74 #define PCF50633_REG_INT5 0x06 |
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75 |
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76 #define PCF50633_REG_INT1M 0x07 |
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77 #define PCF50633_REG_INT2M 0x08 |
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78 #define PCF50633_REG_INT3M 0x09 |
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79 #define PCF50633_REG_INT4M 0x0a |
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80 #define PCF50633_REG_INT5M 0x0b |
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81 |
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82 enum { |
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83 /* Chip IRQs */ |
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84 PCF50633_IRQ_ADPINS, |
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85 PCF50633_IRQ_ADPREM, |
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86 PCF50633_IRQ_USBINS, |
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87 PCF50633_IRQ_USBREM, |
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88 PCF50633_IRQ_RESERVED1, |
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89 PCF50633_IRQ_RESERVED2, |
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90 PCF50633_IRQ_ALARM, |
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91 PCF50633_IRQ_SECOND, |
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92 PCF50633_IRQ_ONKEYR, |
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93 PCF50633_IRQ_ONKEYF, |
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94 PCF50633_IRQ_EXTON1R, |
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95 PCF50633_IRQ_EXTON1F, |
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96 PCF50633_IRQ_EXTON2R, |
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97 PCF50633_IRQ_EXTON2F, |
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98 PCF50633_IRQ_EXTON3R, |
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99 PCF50633_IRQ_EXTON3F, |
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100 PCF50633_IRQ_BATFULL, |
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101 PCF50633_IRQ_CHGHALT, |
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102 PCF50633_IRQ_THLIMON, |
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103 PCF50633_IRQ_THLIMOFF, |
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104 PCF50633_IRQ_USBLIMON, |
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105 PCF50633_IRQ_USBLIMOFF, |
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106 PCF50633_IRQ_ADCRDY, |
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107 PCF50633_IRQ_ONKEY1S, |
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108 PCF50633_IRQ_LOWSYS, |
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109 PCF50633_IRQ_LOWBAT, |
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110 PCF50633_IRQ_HIGHTMP, |
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111 PCF50633_IRQ_AUTOPWRFAIL, |
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112 PCF50633_IRQ_DWN1PWRFAIL, |
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113 PCF50633_IRQ_DWN2PWRFAIL, |
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114 PCF50633_IRQ_LEDPWRFAIL, |
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115 PCF50633_IRQ_LEDOVP, |
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116 PCF50633_IRQ_LDO1PWRFAIL, |
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117 PCF50633_IRQ_LDO2PWRFAIL, |
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118 PCF50633_IRQ_LDO3PWRFAIL, |
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119 PCF50633_IRQ_LDO4PWRFAIL, |
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120 PCF50633_IRQ_LDO5PWRFAIL, |
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121 PCF50633_IRQ_LDO6PWRFAIL, |
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122 PCF50633_IRQ_HCLDOPWRFAIL, |
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123 PCF50633_IRQ_HCLDOOVL, |
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124 |
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125 /* Always last */ |
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126 PCF50633_NUM_IRQ, |
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127 }; |
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128 |
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129 struct pcf50633 { |
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130 struct device *dev; |
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131 struct i2c_client *i2c_client; |
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132 |
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133 struct pcf50633_platform_data *pdata; |
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134 int irq; |
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135 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; |
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136 struct work_struct irq_work; |
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137 struct mutex lock; |
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138 |
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139 u8 mask_regs[5]; |
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140 |
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141 u8 suspend_irq_masks[5]; |
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142 u8 resume_reason[5]; |
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143 int is_suspended; |
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144 |
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145 int onkey1s_held; |
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146 |
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147 struct platform_device *rtc_pdev; |
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148 struct platform_device *mbc_pdev; |
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149 struct platform_device *adc_pdev; |
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150 struct platform_device *input_pdev; |
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151 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; |
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152 }; |
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153 |
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154 enum pcf50633_reg_int1 { |
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155 PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ |
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156 PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ |
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157 PCF50633_INT1_USBINS = 0x04, /* USB inserted */ |
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158 PCF50633_INT1_USBREM = 0x08, /* USB removed */ |
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159 /* reserved */ |
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160 PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ |
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161 PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ |
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162 }; |
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163 |
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164 enum pcf50633_reg_int2 { |
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165 PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ |
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166 PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ |
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167 PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ |
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168 PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ |
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169 PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ |
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170 PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ |
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171 PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ |
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172 PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ |
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173 }; |
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174 |
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175 enum pcf50633_reg_int3 { |
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176 PCF50633_INT3_BATFULL = 0x01, /* Battery full */ |
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177 PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ |
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178 PCF50633_INT3_THLIMON = 0x04, |
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179 PCF50633_INT3_THLIMOFF = 0x08, |
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180 PCF50633_INT3_USBLIMON = 0x10, |
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181 PCF50633_INT3_USBLIMOFF = 0x20, |
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182 PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ |
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183 PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ |
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184 }; |
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185 |
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186 enum pcf50633_reg_int4 { |
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187 PCF50633_INT4_LOWSYS = 0x01, |
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188 PCF50633_INT4_LOWBAT = 0x02, |
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189 PCF50633_INT4_HIGHTMP = 0x04, |
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190 PCF50633_INT4_AUTOPWRFAIL = 0x08, |
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191 PCF50633_INT4_DWN1PWRFAIL = 0x10, |
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192 PCF50633_INT4_DWN2PWRFAIL = 0x20, |
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193 PCF50633_INT4_LEDPWRFAIL = 0x40, |
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194 PCF50633_INT4_LEDOVP = 0x80, |
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195 }; |
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196 |
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197 enum pcf50633_reg_int5 { |
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198 PCF50633_INT5_LDO1PWRFAIL = 0x01, |
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199 PCF50633_INT5_LDO2PWRFAIL = 0x02, |
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200 PCF50633_INT5_LDO3PWRFAIL = 0x04, |
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201 PCF50633_INT5_LDO4PWRFAIL = 0x08, |
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202 PCF50633_INT5_LDO5PWRFAIL = 0x10, |
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203 PCF50633_INT5_LDO6PWRFAIL = 0x20, |
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204 PCF50633_INT5_HCLDOPWRFAIL = 0x40, |
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205 PCF50633_INT5_HCLDOOVL = 0x80, |
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206 }; |
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207 |
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208 /* misc. registers */ |
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209 #define PCF50633_REG_OOCSHDWN 0x0c |
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210 |
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211 /* LED registers */ |
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212 #define PCF50633_REG_LEDOUT 0x28 |
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213 #define PCF50633_REG_LEDENA 0x29 |
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214 #define PCF50633_REG_LEDCTL 0x2a |
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215 #define PCF50633_REG_LEDDIM 0x2b |
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216 |
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217 #endif |
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218 |