7 #define VTD_PAGE_SHIFT (12) |
7 #define VTD_PAGE_SHIFT (12) |
8 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) |
8 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) |
9 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) |
9 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) |
10 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) |
10 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) |
11 |
11 |
12 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
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13 #define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK) |
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14 #define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK) |
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15 |
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16 |
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17 /* |
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18 * 0: Present |
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19 * 1-11: Reserved |
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20 * 12-63: Context Ptr (12 - (haw-1)) |
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21 * 64-127: Reserved |
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22 */ |
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23 struct root_entry { |
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24 u64 val; |
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25 u64 rsvd1; |
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26 }; |
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27 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) |
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28 static inline bool root_present(struct root_entry *root) |
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29 { |
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30 return (root->val & 1); |
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31 } |
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32 static inline void set_root_present(struct root_entry *root) |
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33 { |
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34 root->val |= 1; |
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35 } |
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36 static inline void set_root_value(struct root_entry *root, unsigned long value) |
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37 { |
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38 root->val |= value & VTD_PAGE_MASK; |
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39 } |
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40 |
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41 struct context_entry; |
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42 static inline struct context_entry * |
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43 get_context_addr_from_root(struct root_entry *root) |
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44 { |
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45 return (struct context_entry *) |
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46 (root_present(root)?phys_to_virt( |
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47 root->val & VTD_PAGE_MASK) : |
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48 NULL); |
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49 } |
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50 |
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51 /* |
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52 * low 64 bits: |
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53 * 0: present |
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54 * 1: fault processing disable |
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55 * 2-3: translation type |
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56 * 12-63: address space root |
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57 * high 64 bits: |
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58 * 0-2: address width |
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59 * 3-6: aval |
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60 * 8-23: domain id |
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61 */ |
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62 struct context_entry { |
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63 u64 lo; |
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64 u64 hi; |
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65 }; |
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66 #define context_present(c) ((c).lo & 1) |
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67 #define context_fault_disable(c) (((c).lo >> 1) & 1) |
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68 #define context_translation_type(c) (((c).lo >> 2) & 3) |
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69 #define context_address_root(c) ((c).lo & VTD_PAGE_MASK) |
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70 #define context_address_width(c) ((c).hi & 7) |
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71 #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1)) |
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72 |
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73 #define context_set_present(c) do {(c).lo |= 1;} while (0) |
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74 #define context_set_fault_enable(c) \ |
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75 do {(c).lo &= (((u64)-1) << 2) | 1;} while (0) |
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76 #define context_set_translation_type(c, val) \ |
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77 do { \ |
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78 (c).lo &= (((u64)-1) << 4) | 3; \ |
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79 (c).lo |= ((val) & 3) << 2; \ |
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80 } while (0) |
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81 #define CONTEXT_TT_MULTI_LEVEL 0 |
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82 #define context_set_address_root(c, val) \ |
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83 do {(c).lo |= (val) & VTD_PAGE_MASK; } while (0) |
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84 #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0) |
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85 #define context_set_domain_id(c, val) \ |
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86 do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) |
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87 #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) |
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88 |
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89 /* |
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90 * 0: readable |
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91 * 1: writable |
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92 * 2-6: reserved |
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93 * 7: super page |
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94 * 8-11: available |
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95 * 12-63: Host physcial address |
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96 */ |
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97 struct dma_pte { |
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98 u64 val; |
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99 }; |
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100 #define dma_clear_pte(p) do {(p).val = 0;} while (0) |
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101 |
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102 #define DMA_PTE_READ (1) |
12 #define DMA_PTE_READ (1) |
103 #define DMA_PTE_WRITE (2) |
13 #define DMA_PTE_WRITE (2) |
104 |
14 |
105 #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) |
15 struct intel_iommu; |
106 #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) |
16 struct dmar_domain; |
107 #define dma_set_pte_prot(p, prot) \ |
17 struct root_entry; |
108 do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) |
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109 #define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK) |
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110 #define dma_set_pte_addr(p, addr) do {\ |
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111 (p).val |= ((addr) & VTD_PAGE_MASK); } while (0) |
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112 #define dma_pte_present(p) (((p).val & 3) != 0) |
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113 |
18 |
114 struct intel_iommu; |
19 extern void free_dmar_iommu(struct intel_iommu *iommu); |
115 |
20 |
116 struct dmar_domain { |
21 #ifdef CONFIG_DMAR |
117 int id; /* domain id */ |
22 extern int iommu_calculate_agaw(struct intel_iommu *iommu); |
118 struct intel_iommu *iommu; /* back pointer to owning iommu */ |
23 #else |
119 |
24 static inline int iommu_calculate_agaw(struct intel_iommu *iommu) |
120 struct list_head devices; /* all devices' list */ |
25 { |
121 struct iova_domain iovad; /* iova's that belong to this domain */ |
26 return 0; |
122 |
27 } |
123 struct dma_pte *pgd; /* virtual address */ |
28 #endif |
124 spinlock_t mapping_lock; /* page table lock */ |
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125 int gaw; /* max guest address width */ |
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126 |
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127 /* adjusted guest address width, 0 is level 2 30-bit */ |
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128 int agaw; |
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129 |
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130 #define DOMAIN_FLAG_MULTIPLE_DEVICES 1 |
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131 int flags; |
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132 }; |
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133 |
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134 /* PCI domain-device relationship */ |
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135 struct device_domain_info { |
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136 struct list_head link; /* link to domain siblings */ |
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137 struct list_head global; /* link to global list */ |
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138 u8 bus; /* PCI bus numer */ |
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139 u8 devfn; /* PCI devfn number */ |
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140 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ |
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141 struct dmar_domain *domain; /* pointer to domain */ |
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142 }; |
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143 |
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144 extern int init_dmars(void); |
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145 extern void free_dmar_iommu(struct intel_iommu *iommu); |
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146 |
29 |
147 extern int dmar_disabled; |
30 extern int dmar_disabled; |
148 |
31 |
149 #ifndef CONFIG_DMAR_GFX_WA |
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150 static inline void iommu_prepare_gfx_mapping(void) |
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151 { |
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152 return; |
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153 } |
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154 #endif /* !CONFIG_DMAR_GFX_WA */ |
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155 |
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156 #endif |
32 #endif |