111 /* |
111 /* |
112 * The largest possible NASID of a C or M brick (+ 2) |
112 * The largest possible NASID of a C or M brick (+ 2) |
113 */ |
113 */ |
114 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) |
114 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) |
115 |
115 |
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116 struct uv_scir_s { |
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117 struct timer_list timer; |
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118 unsigned long offset; |
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119 unsigned long last; |
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120 unsigned long idle_on; |
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121 unsigned long idle_off; |
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122 unsigned char state; |
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123 unsigned char enabled; |
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124 }; |
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125 |
116 /* |
126 /* |
117 * The following defines attributes of the HUB chip. These attributes are |
127 * The following defines attributes of the HUB chip. These attributes are |
118 * frequently referenced and are kept in the per-cpu data areas of each cpu. |
128 * frequently referenced and are kept in the per-cpu data areas of each cpu. |
119 * They are kept together in a struct to minimize cache misses. |
129 * They are kept together in a struct to minimize cache misses. |
120 */ |
130 */ |
121 struct uv_hub_info_s { |
131 struct uv_hub_info_s { |
122 unsigned long global_mmr_base; |
132 unsigned long global_mmr_base; |
123 unsigned long gpa_mask; |
133 unsigned long gpa_mask; |
124 unsigned long gnode_upper; |
134 unsigned long gnode_upper; |
125 unsigned long lowmem_remap_top; |
135 unsigned long lowmem_remap_top; |
126 unsigned long lowmem_remap_base; |
136 unsigned long lowmem_remap_base; |
127 unsigned short pnode; |
137 unsigned short pnode; |
128 unsigned short pnode_mask; |
138 unsigned short pnode_mask; |
129 unsigned short coherency_domain_number; |
139 unsigned short coherency_domain_number; |
130 unsigned short numa_blade_id; |
140 unsigned short numa_blade_id; |
131 unsigned char blade_processor_id; |
141 unsigned char blade_processor_id; |
132 unsigned char m_val; |
142 unsigned char m_val; |
133 unsigned char n_val; |
143 unsigned char n_val; |
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144 struct uv_scir_s scir; |
134 }; |
145 }; |
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146 |
135 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
147 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
136 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) |
148 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) |
137 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) |
149 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) |
138 |
150 |
139 /* |
151 /* |
161 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
173 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
162 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
174 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
163 |
175 |
164 #define UV_APIC_PNODE_SHIFT 6 |
176 #define UV_APIC_PNODE_SHIFT 6 |
165 |
177 |
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178 /* Local Bus from cpu's perspective */ |
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179 #define LOCAL_BUS_BASE 0x1c00000 |
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180 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) |
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181 |
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182 /* |
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183 * System Controller Interface Reg |
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184 * |
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185 * Note there are NO leds on a UV system. This register is only |
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186 * used by the system controller to monitor system-wide operation. |
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187 * There are 64 regs per node. With Nahelem cpus (2 cores per node, |
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188 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on |
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189 * a node. |
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190 * |
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191 * The window is located at top of ACPI MMR space |
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192 */ |
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193 #define SCIR_WINDOW_COUNT 64 |
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194 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ |
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195 LOCAL_BUS_SIZE - \ |
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196 SCIR_WINDOW_COUNT) |
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197 |
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198 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ |
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199 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ |
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200 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ |
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201 |
166 /* |
202 /* |
167 * Macros for converting between kernel virtual addresses, socket local physical |
203 * Macros for converting between kernel virtual addresses, socket local physical |
168 * addresses, and UV global physical addresses. |
204 * addresses, and UV global physical addresses. |
169 * Note: use the standard __pa() & __va() macros for converting |
205 * Note: use the standard __pa() & __va() macros for converting |
170 * between socket virtual and socket physical addresses. |
206 * between socket virtual and socket physical addresses. |
172 |
208 |
173 /* socket phys RAM --> UV global physical address */ |
209 /* socket phys RAM --> UV global physical address */ |
174 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) |
210 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) |
175 { |
211 { |
176 if (paddr < uv_hub_info->lowmem_remap_top) |
212 if (paddr < uv_hub_info->lowmem_remap_top) |
177 paddr += uv_hub_info->lowmem_remap_base; |
213 paddr |= uv_hub_info->lowmem_remap_base; |
178 return paddr | uv_hub_info->gnode_upper; |
214 return paddr | uv_hub_info->gnode_upper; |
179 } |
215 } |
180 |
216 |
181 |
217 |
182 /* socket virtual --> UV global physical address */ |
218 /* socket virtual --> UV global physical address */ |
183 static inline unsigned long uv_gpa(void *v) |
219 static inline unsigned long uv_gpa(void *v) |
184 { |
220 { |
185 return __pa(v) | uv_hub_info->gnode_upper; |
221 return uv_soc_phys_ram_to_gpa(__pa(v)); |
186 } |
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187 |
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188 /* socket virtual --> UV global physical address */ |
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189 static inline void *uv_vgpa(void *v) |
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190 { |
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191 return (void *)uv_gpa(v); |
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192 } |
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193 |
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194 /* UV global physical address --> socket virtual */ |
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195 static inline void *uv_va(unsigned long gpa) |
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196 { |
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197 return __va(gpa & uv_hub_info->gpa_mask); |
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198 } |
222 } |
199 |
223 |
200 /* pnode, offset --> socket virtual */ |
224 /* pnode, offset --> socket virtual */ |
201 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) |
225 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) |
202 { |
226 { |
273 } |
297 } |
274 |
298 |
275 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) |
299 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) |
276 { |
300 { |
277 *uv_local_mmr_address(offset) = val; |
301 *uv_local_mmr_address(offset) = val; |
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302 } |
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303 |
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304 static inline unsigned char uv_read_local_mmr8(unsigned long offset) |
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305 { |
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306 return *((unsigned char *)uv_local_mmr_address(offset)); |
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307 } |
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308 |
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309 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) |
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310 { |
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311 *((unsigned char *)uv_local_mmr_address(offset)) = val; |
278 } |
312 } |
279 |
313 |
280 /* |
314 /* |
281 * Structures and definitions for converting between cpu, node, pnode, and blade |
315 * Structures and definitions for converting between cpu, node, pnode, and blade |
282 * numbers. |
316 * numbers. |
349 static inline int uv_num_possible_blades(void) |
383 static inline int uv_num_possible_blades(void) |
350 { |
384 { |
351 return uv_possible_blades; |
385 return uv_possible_blades; |
352 } |
386 } |
353 |
387 |
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388 /* Update SCIR state */ |
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389 static inline void uv_set_scir_bits(unsigned char value) |
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390 { |
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391 if (uv_hub_info->scir.state != value) { |
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392 uv_hub_info->scir.state = value; |
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393 uv_write_local_mmr8(uv_hub_info->scir.offset, value); |
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394 } |
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395 } |
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396 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) |
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397 { |
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398 if (uv_cpu_hub_info(cpu)->scir.state != value) { |
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399 uv_cpu_hub_info(cpu)->scir.state = value; |
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400 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value); |
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401 } |
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402 } |
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403 |
354 #endif /* _ASM_X86_UV_UV_HUB_H */ |
404 #endif /* _ASM_X86_UV_UV_HUB_H */ |
355 |
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