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1 /* |
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2 * Hardware-specific External Interface I/O core definitions |
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3 * for the BCM47xx family of SiliconBackplane-based chips. |
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4 * |
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5 * The External Interface core supports a total of three external chip selects |
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6 * supporting external interfaces. One of the external chip selects is |
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7 * used for Flash, one is used for PCMCIA, and the other may be |
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8 * programmed to support either a synchronous interface or an |
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9 * asynchronous interface. The asynchronous interface can be used to |
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10 * support external devices such as UARTs and the BCM2019 Bluetooth |
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11 * baseband processor. |
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12 * The external interface core also contains 2 on-chip 16550 UARTs, clock |
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13 * frequency control, a watchdog interrupt timer, and a GPIO interface. |
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14 * |
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15 * Copyright 2005, Broadcom Corporation |
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16 * Copyright 2006, Michael Buesch |
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17 * |
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18 * Licensed under the GPL version 2. See COPYING for details. |
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19 */ |
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20 #ifndef LINUX_SSB_EXTIFCORE_H_ |
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21 #define LINUX_SSB_EXTIFCORE_H_ |
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22 |
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23 /* external interface address space */ |
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24 #define SSB_EXTIF_PCMCIA_MEMBASE(x) (x) |
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25 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000) |
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26 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000) |
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27 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000) |
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28 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000) |
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29 |
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30 #define SSB_EXTIF_NR_GPIOOUT 5 |
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31 /* GPIO NOTE: |
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32 * The multiple instances of output and output enable registers |
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33 * are present to allow driver software for multiple cores to control |
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34 * gpio outputs without needing to share a single register pair. |
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35 * Use the following helper macro to get a register offset value. |
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36 */ |
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37 #define SSB_EXTIF_GPIO_OUT(index) ({ \ |
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38 BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \ |
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39 SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8); \ |
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40 }) |
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41 #define SSB_EXTIF_GPIO_OUTEN(index) ({ \ |
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42 BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \ |
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43 SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8); \ |
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44 }) |
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45 |
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46 /** EXTIF core registers **/ |
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47 |
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48 #define SSB_EXTIF_CTL 0x0000 |
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49 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */ |
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50 #define SSB_EXTIF_EXTSTAT 0x0004 |
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51 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */ |
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52 #define SSB_EXTIF_EXTSTAT_EIRQPIN (1 << 1) /* External interrupt pin (ro) */ |
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53 #define SSB_EXTIF_EXTSTAT_GPIOIRQPIN (1 << 2) /* GPIO interrupt pin (ro) */ |
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54 #define SSB_EXTIF_PCMCIA_CFG 0x0010 |
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55 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014 |
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56 #define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018 |
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57 #define SSB_EXTIF_PCMCIA_IOWAIT 0x001C |
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58 #define SSB_EXTIF_PROG_CFG 0x0020 |
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59 #define SSB_EXTIF_PROG_WAITCNT 0x0024 |
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60 #define SSB_EXTIF_FLASH_CFG 0x0028 |
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61 #define SSB_EXTIF_FLASH_WAITCNT 0x002C |
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62 #define SSB_EXTIF_WATCHDOG 0x0040 |
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63 #define SSB_EXTIF_CLOCK_N 0x0044 |
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64 #define SSB_EXTIF_CLOCK_SB 0x0048 |
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65 #define SSB_EXTIF_CLOCK_PCI 0x004C |
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66 #define SSB_EXTIF_CLOCK_MII 0x0050 |
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67 #define SSB_EXTIF_GPIO_IN 0x0060 |
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68 #define SSB_EXTIF_GPIO_OUT_BASE 0x0064 |
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69 #define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068 |
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70 #define SSB_EXTIF_EJTAG_OUTEN 0x0090 |
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71 #define SSB_EXTIF_GPIO_INTPOL 0x0094 |
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72 #define SSB_EXTIF_GPIO_INTMASK 0x0098 |
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73 #define SSB_EXTIF_UART_DATA 0x0300 |
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74 #define SSB_EXTIF_UART_TIMER 0x0310 |
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75 #define SSB_EXTIF_UART_FCR 0x0320 |
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76 #define SSB_EXTIF_UART_LCR 0x0330 |
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77 #define SSB_EXTIF_UART_MCR 0x0340 |
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78 #define SSB_EXTIF_UART_LSR 0x0350 |
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79 #define SSB_EXTIF_UART_MSR 0x0360 |
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80 #define SSB_EXTIF_UART_SCRATCH 0x0370 |
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81 |
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82 |
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83 |
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84 |
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85 /* pcmcia/prog/flash_config */ |
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86 #define SSB_EXTCFG_EN (1 << 0) /* enable */ |
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87 #define SSB_EXTCFG_MODE 0xE /* mode */ |
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88 #define SSB_EXTCFG_MODE_SHIFT 1 |
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89 #define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */ |
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90 #define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */ |
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91 #define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */ |
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92 #define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */ |
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93 #define SSB_EXTCFG_BSWAP (1 << 5) /* byteswap */ |
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94 #define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */ |
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95 #define SSB_EXTCFG_CLKDIV_SHIFT 6 |
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96 #define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */ |
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97 #define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */ |
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98 #define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */ |
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99 #define SSB_EXTCFG_CLKEN (1 << 8) /* clock enable */ |
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100 #define SSB_EXTCFG_STROBE (1 << 9) /* size/bytestrobe (synch only) */ |
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101 |
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102 /* pcmcia_memwait */ |
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103 #define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */ |
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104 #define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */ |
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105 #define SSB_PCMCIA_MEMW_1_SHIFT 8 |
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106 #define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */ |
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107 #define SSB_PCMCIA_MEMW_2_SHIFT 16 |
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108 #define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */ |
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109 #define SSB_PCMCIA_MEMW_3_SHIFT 24 |
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110 |
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111 /* pcmcia_attrwait */ |
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112 #define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */ |
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113 #define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */ |
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114 #define SSB_PCMCIA_ATTW_1_SHIFT 8 |
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115 #define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */ |
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116 #define SSB_PCMCIA_ATTW_2_SHIFT 16 |
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117 #define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */ |
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118 #define SSB_PCMCIA_ATTW_3_SHIFT 24 |
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119 |
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120 /* pcmcia_iowait */ |
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121 #define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */ |
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122 #define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */ |
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123 #define SSB_PCMCIA_IOW_1_SHIFT 8 |
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124 #define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */ |
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125 #define SSB_PCMCIA_IOW_2_SHIFT 16 |
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126 #define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */ |
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127 #define SSB_PCMCIA_IOW_3_SHIFT 24 |
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128 |
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129 /* prog_waitcount */ |
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130 #define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */ |
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131 #define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */ |
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132 #define SSB_PROG_WCNT_1_SHIFT 8 |
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133 #define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */ |
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134 #define SSB_PROG_WCNT_2_SHIFT 16 |
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135 #define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */ |
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136 #define SSB_PROG_WCNT_3_SHIFT 24 |
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137 |
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138 #define SSB_PROG_W0 0x0000000C |
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139 #define SSB_PROG_W1 0x00000A00 |
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140 #define SSB_PROG_W2 0x00020000 |
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141 #define SSB_PROG_W3 0x01000000 |
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142 |
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143 /* flash_waitcount */ |
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144 #define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */ |
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145 #define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */ |
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146 #define SSB_FLASH_WCNT_1_SHIFT 8 |
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147 #define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */ |
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148 #define SSB_FLASH_WCNT_2_SHIFT 16 |
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149 #define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */ |
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150 #define SSB_FLASH_WCNT_3_SHIFT 24 |
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151 |
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152 /* watchdog */ |
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153 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ |
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154 |
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155 |
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156 |
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157 #ifdef CONFIG_SSB_DRIVER_EXTIF |
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158 |
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159 struct ssb_extif { |
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160 struct ssb_device *dev; |
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161 }; |
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162 |
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163 static inline bool ssb_extif_available(struct ssb_extif *extif) |
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164 { |
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165 return (extif->dev != NULL); |
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166 } |
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167 |
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168 extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif, |
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169 u32 *plltype, u32 *n, u32 *m); |
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170 |
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171 extern void ssb_extif_timing_init(struct ssb_extif *extif, |
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172 unsigned long ns); |
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173 |
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174 extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, |
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175 u32 ticks); |
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176 |
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177 /* Extif GPIO pin access */ |
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178 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); |
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179 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value); |
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180 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value); |
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181 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value); |
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182 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value); |
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183 |
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184 #ifdef CONFIG_SSB_SERIAL |
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185 extern int ssb_extif_serial_init(struct ssb_extif *extif, |
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186 struct ssb_serial_port *ports); |
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187 #endif /* CONFIG_SSB_SERIAL */ |
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188 |
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189 |
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190 #else /* CONFIG_SSB_DRIVER_EXTIF */ |
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191 /* extif disabled */ |
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192 |
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193 struct ssb_extif { |
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194 }; |
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195 |
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196 static inline bool ssb_extif_available(struct ssb_extif *extif) |
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197 { |
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198 return 0; |
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199 } |
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200 |
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201 static inline |
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202 void ssb_extif_get_clockcontrol(struct ssb_extif *extif, |
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203 u32 *plltype, u32 *n, u32 *m) |
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204 { |
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205 } |
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206 |
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207 static inline |
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208 void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, |
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209 u32 ticks) |
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210 { |
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211 } |
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212 |
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213 #endif /* CONFIG_SSB_DRIVER_EXTIF */ |
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214 #endif /* LINUX_SSB_EXTIFCORE_H_ */ |