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1 /* |
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2 * include/linux/spi/spidev.h |
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3 * |
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4 * Copyright (C) 2006 SWAPP |
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5 * Andrea Paterniani <a.paterniani@swapp-eng.it> |
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6 * |
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7 * This program is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * This program is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with this program; if not, write to the Free Software |
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19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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20 */ |
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21 |
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22 #ifndef SPIDEV_H |
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23 #define SPIDEV_H |
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24 |
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25 |
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26 /* User space versions of kernel symbols for SPI clocking modes, |
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27 * matching <linux/spi/spi.h> |
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28 */ |
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29 |
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30 #define SPI_CPHA 0x01 |
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31 #define SPI_CPOL 0x02 |
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32 |
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33 #define SPI_MODE_0 (0|0) |
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34 #define SPI_MODE_1 (0|SPI_CPHA) |
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35 #define SPI_MODE_2 (SPI_CPOL|0) |
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36 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) |
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37 |
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38 #define SPI_CS_HIGH 0x04 |
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39 #define SPI_LSB_FIRST 0x08 |
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40 #define SPI_3WIRE 0x10 |
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41 #define SPI_LOOP 0x20 |
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42 |
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43 /*---------------------------------------------------------------------------*/ |
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44 |
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45 /* IOCTL commands */ |
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46 |
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47 #define SPI_IOC_MAGIC 'k' |
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48 |
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49 /** |
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50 * struct spi_ioc_transfer - describes a single SPI transfer |
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51 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. |
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52 * If no data is provided, zeroes are shifted out. |
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53 * @rx_buf: Holds pointer to userspace buffer for receive data, or null. |
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54 * @len: Length of tx and rx buffers, in bytes. |
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55 * @speed_hz: Temporary override of the device's bitrate. |
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56 * @bits_per_word: Temporary override of the device's wordsize. |
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57 * @delay_usecs: If nonzero, how long to delay after the last bit transfer |
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58 * before optionally deselecting the device before the next transfer. |
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59 * @cs_change: True to deselect device before starting the next transfer. |
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60 * |
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61 * This structure is mapped directly to the kernel spi_transfer structure; |
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62 * the fields have the same meanings, except of course that the pointers |
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63 * are in a different address space (and may be of different sizes in some |
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64 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel). |
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65 * Zero-initialize the structure, including currently unused fields, to |
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66 * accomodate potential future updates. |
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67 * |
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68 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync(). |
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69 * Pass it an array of related transfers, they'll execute together. |
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70 * Each transfer may be half duplex (either direction) or full duplex. |
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71 * |
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72 * struct spi_ioc_transfer mesg[4]; |
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73 * ... |
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74 * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg); |
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75 * |
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76 * So for example one transfer might send a nine bit command (right aligned |
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77 * in a 16-bit word), the next could read a block of 8-bit data before |
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78 * terminating that command by temporarily deselecting the chip; the next |
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79 * could send a different nine bit command (re-selecting the chip), and the |
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80 * last transfer might write some register values. |
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81 */ |
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82 struct spi_ioc_transfer { |
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83 __u64 tx_buf; |
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84 __u64 rx_buf; |
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85 |
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86 __u32 len; |
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87 __u32 speed_hz; |
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88 |
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89 __u16 delay_usecs; |
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90 __u8 bits_per_word; |
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91 __u8 cs_change; |
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92 __u32 pad; |
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93 |
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94 /* If the contents of 'struct spi_ioc_transfer' ever change |
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95 * incompatibly, then the ioctl number (currently 0) must change; |
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96 * ioctls with constant size fields get a bit more in the way of |
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97 * error checking than ones (like this) where that field varies. |
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98 * |
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99 * NOTE: struct layout is the same in 64bit and 32bit userspace. |
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100 */ |
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101 }; |
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102 |
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103 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ |
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104 #define SPI_MSGSIZE(N) \ |
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105 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ |
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106 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) |
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107 #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) |
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108 |
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109 |
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110 /* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */ |
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111 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8) |
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112 #define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8) |
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113 |
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114 /* Read / Write SPI bit justification */ |
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115 #define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8) |
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116 #define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8) |
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117 |
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118 /* Read / Write SPI device word length (1..N) */ |
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119 #define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8) |
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120 #define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8) |
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121 |
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122 /* Read / Write SPI device default max speed hz */ |
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123 #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) |
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124 #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) |
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125 |
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126 |
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127 |
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128 #endif /* SPIDEV_H */ |