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1 /* |
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2 * SuperH FLCTL nand controller |
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3 * |
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4 * Copyright © 2008 Renesas Solutions Corp. |
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5 * |
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6 * This program is free software; you can redistribute it and/or modify |
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7 * it under the terms of the GNU General Public License as published by |
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8 * the Free Software Foundation; version 2 of the License. |
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9 * |
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10 * This program is distributed in the hope that it will be useful, |
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 * GNU General Public License for more details. |
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14 * |
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15 * You should have received a copy of the GNU General Public License |
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16 * along with this program; if not, write to the Free Software |
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17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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18 */ |
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19 |
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20 #ifndef __SH_FLCTL_H__ |
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21 #define __SH_FLCTL_H__ |
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22 |
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23 #include <linux/mtd/mtd.h> |
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24 #include <linux/mtd/nand.h> |
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25 #include <linux/mtd/partitions.h> |
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26 |
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27 /* FLCTL registers */ |
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28 #define FLCMNCR(f) (f->reg + 0x0) |
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29 #define FLCMDCR(f) (f->reg + 0x4) |
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30 #define FLCMCDR(f) (f->reg + 0x8) |
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31 #define FLADR(f) (f->reg + 0xC) |
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32 #define FLADR2(f) (f->reg + 0x3C) |
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33 #define FLDATAR(f) (f->reg + 0x10) |
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34 #define FLDTCNTR(f) (f->reg + 0x14) |
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35 #define FLINTDMACR(f) (f->reg + 0x18) |
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36 #define FLBSYTMR(f) (f->reg + 0x1C) |
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37 #define FLBSYCNT(f) (f->reg + 0x20) |
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38 #define FLDTFIFO(f) (f->reg + 0x24) |
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39 #define FLECFIFO(f) (f->reg + 0x28) |
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40 #define FLTRCR(f) (f->reg + 0x2C) |
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41 #define FL4ECCRESULT0(f) (f->reg + 0x80) |
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42 #define FL4ECCRESULT1(f) (f->reg + 0x84) |
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43 #define FL4ECCRESULT2(f) (f->reg + 0x88) |
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44 #define FL4ECCRESULT3(f) (f->reg + 0x8C) |
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45 #define FL4ECCCR(f) (f->reg + 0x90) |
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46 #define FL4ECCCNT(f) (f->reg + 0x94) |
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47 #define FLERRADR(f) (f->reg + 0x98) |
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48 |
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49 /* FLCMNCR control bits */ |
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50 #define ECCPOS2 (0x1 << 25) |
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51 #define _4ECCCNTEN (0x1 << 24) |
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52 #define _4ECCEN (0x1 << 23) |
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53 #define _4ECCCORRECT (0x1 << 22) |
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54 #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ |
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55 #define QTSEL_E (0x1 << 17) |
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56 #define ENDIAN (0x1 << 16) /* 1 = little endian */ |
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57 #define FCKSEL_E (0x1 << 15) |
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58 #define ECCPOS_00 (0x00 << 12) |
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59 #define ECCPOS_01 (0x01 << 12) |
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60 #define ECCPOS_02 (0x02 << 12) |
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61 #define ACM_SACCES_MODE (0x01 << 10) |
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62 #define NANWF_E (0x1 << 9) |
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63 #define SE_D (0x1 << 8) /* Spare area disable */ |
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64 #define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */ |
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65 #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ |
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66 #define TYPESEL_SET (0x1 << 0) |
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67 |
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68 /* FLCMDCR control bits */ |
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69 #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ |
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70 #define ADRMD_E (0x1 << 26) /* Sector address access */ |
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71 #define CDSRC_E (0x1 << 25) /* Data buffer selection */ |
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72 #define DOSR_E (0x1 << 24) /* Status read check */ |
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73 #define SELRW (0x1 << 21) /* 0:read 1:write */ |
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74 #define DOADR_E (0x1 << 20) /* Address stage execute */ |
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75 #define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */ |
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76 #define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */ |
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77 #define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */ |
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78 #define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */ |
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79 #define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ |
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80 #define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ |
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81 |
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82 /* FLTRCR control bits */ |
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83 #define TRSTRT (0x1 << 0) /* translation start */ |
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84 #define TREND (0x1 << 1) /* translation end */ |
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85 |
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86 /* FL4ECCCR control bits */ |
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87 #define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ |
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88 #define _4ECCEND (0x1 << 1) /* 4 symbols end */ |
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89 #define _4ECCEXST (0x1 << 0) /* 4 symbols exist */ |
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90 |
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91 #define INIT_FL4ECCRESULT_VAL 0x03FF03FF |
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92 #define LOOP_TIMEOUT_MAX 0x00010000 |
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93 |
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94 #define mtd_to_flctl(mtd) container_of(mtd, struct sh_flctl, mtd) |
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95 |
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96 struct sh_flctl { |
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97 struct mtd_info mtd; |
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98 struct nand_chip chip; |
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99 void __iomem *reg; |
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100 |
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101 uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */ |
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102 int read_bytes; |
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103 int index; |
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104 int seqin_column; /* column in SEQIN cmd */ |
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105 int seqin_page_addr; /* page_addr in SEQIN cmd */ |
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106 uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */ |
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107 int erase1_page_addr; /* page_addr in ERASE1 cmd */ |
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108 uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ |
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109 uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ |
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110 |
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111 int hwecc_cant_correct[4]; |
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112 |
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113 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ |
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114 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ |
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115 }; |
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116 |
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117 struct sh_flctl_platform_data { |
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118 struct mtd_partition *parts; |
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119 int nr_parts; |
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120 unsigned long flcmncr_val; |
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121 |
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122 unsigned has_hwecc:1; |
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123 }; |
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124 |
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125 #endif /* __SH_FLCTL_H__ */ |