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1 /* |
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2 * linux/include/linux/mtd/nand.h |
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3 * |
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4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> |
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5 * Steven J. Hill <sjhill@realitydiluted.com> |
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6 * Thomas Gleixner <tglx@linutronix.de> |
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7 * |
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8 * This program is free software; you can redistribute it and/or modify |
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9 * it under the terms of the GNU General Public License version 2 as |
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10 * published by the Free Software Foundation. |
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11 * |
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12 * Info: |
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13 * Contains standard defines and IDs for NAND flash devices |
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14 * |
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15 * Changelog: |
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16 * See git changelog. |
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17 */ |
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18 #ifndef __LINUX_MTD_NAND_H |
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19 #define __LINUX_MTD_NAND_H |
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20 |
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21 #include <linux/wait.h> |
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22 #include <linux/spinlock.h> |
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23 #include <linux/mtd/mtd.h> |
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24 |
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25 struct mtd_info; |
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26 /* Scan and identify a NAND device */ |
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27 extern int nand_scan (struct mtd_info *mtd, int max_chips); |
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28 /* Separate phases of nand_scan(), allowing board driver to intervene |
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29 * and override command or ECC setup according to flash type */ |
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30 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); |
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31 extern int nand_scan_tail(struct mtd_info *mtd); |
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32 |
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33 /* Free resources held by the NAND device */ |
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34 extern void nand_release (struct mtd_info *mtd); |
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35 |
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36 /* Internal helper for board drivers which need to override command function */ |
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37 extern void nand_wait_ready(struct mtd_info *mtd); |
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38 |
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39 /* The maximum number of NAND chips in an array */ |
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40 #define NAND_MAX_CHIPS 8 |
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41 |
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42 /* This constant declares the max. oobsize / page, which |
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43 * is supported now. If you add a chip with bigger oobsize/page |
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44 * adjust this accordingly. |
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45 */ |
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46 #define NAND_MAX_OOBSIZE 64 |
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47 #define NAND_MAX_PAGESIZE 2048 |
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48 |
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49 /* |
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50 * Constants for hardware specific CLE/ALE/NCE function |
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51 * |
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52 * These are bits which can be or'ed to set/clear multiple |
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53 * bits in one go. |
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54 */ |
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55 /* Select the chip by setting nCE to low */ |
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56 #define NAND_NCE 0x01 |
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57 /* Select the command latch by setting CLE to high */ |
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58 #define NAND_CLE 0x02 |
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59 /* Select the address latch by setting ALE to high */ |
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60 #define NAND_ALE 0x04 |
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61 |
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62 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) |
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63 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) |
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64 #define NAND_CTRL_CHANGE 0x80 |
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65 |
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66 /* |
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67 * Standard NAND flash commands |
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68 */ |
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69 #define NAND_CMD_READ0 0 |
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70 #define NAND_CMD_READ1 1 |
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71 #define NAND_CMD_RNDOUT 5 |
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72 #define NAND_CMD_PAGEPROG 0x10 |
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73 #define NAND_CMD_READOOB 0x50 |
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74 #define NAND_CMD_ERASE1 0x60 |
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75 #define NAND_CMD_STATUS 0x70 |
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76 #define NAND_CMD_STATUS_MULTI 0x71 |
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77 #define NAND_CMD_SEQIN 0x80 |
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78 #define NAND_CMD_RNDIN 0x85 |
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79 #define NAND_CMD_READID 0x90 |
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80 #define NAND_CMD_ERASE2 0xd0 |
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81 #define NAND_CMD_RESET 0xff |
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82 |
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83 /* Extended commands for large page devices */ |
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84 #define NAND_CMD_READSTART 0x30 |
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85 #define NAND_CMD_RNDOUTSTART 0xE0 |
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86 #define NAND_CMD_CACHEDPROG 0x15 |
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87 |
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88 /* Extended commands for AG-AND device */ |
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89 /* |
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90 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but |
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91 * there is no way to distinguish that from NAND_CMD_READ0 |
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92 * until the remaining sequence of commands has been completed |
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93 * so add a high order bit and mask it off in the command. |
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94 */ |
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95 #define NAND_CMD_DEPLETE1 0x100 |
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96 #define NAND_CMD_DEPLETE2 0x38 |
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97 #define NAND_CMD_STATUS_MULTI 0x71 |
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98 #define NAND_CMD_STATUS_ERROR 0x72 |
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99 /* multi-bank error status (banks 0-3) */ |
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100 #define NAND_CMD_STATUS_ERROR0 0x73 |
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101 #define NAND_CMD_STATUS_ERROR1 0x74 |
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102 #define NAND_CMD_STATUS_ERROR2 0x75 |
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103 #define NAND_CMD_STATUS_ERROR3 0x76 |
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104 #define NAND_CMD_STATUS_RESET 0x7f |
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105 #define NAND_CMD_STATUS_CLEAR 0xff |
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106 |
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107 #define NAND_CMD_NONE -1 |
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108 |
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109 /* Status bits */ |
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110 #define NAND_STATUS_FAIL 0x01 |
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111 #define NAND_STATUS_FAIL_N1 0x02 |
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112 #define NAND_STATUS_TRUE_READY 0x20 |
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113 #define NAND_STATUS_READY 0x40 |
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114 #define NAND_STATUS_WP 0x80 |
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115 |
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116 /* |
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117 * Constants for ECC_MODES |
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118 */ |
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119 typedef enum { |
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120 NAND_ECC_NONE, |
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121 NAND_ECC_SOFT, |
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122 NAND_ECC_HW, |
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123 NAND_ECC_HW_SYNDROME, |
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124 } nand_ecc_modes_t; |
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125 |
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126 /* |
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127 * Constants for Hardware ECC |
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128 */ |
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129 /* Reset Hardware ECC for read */ |
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130 #define NAND_ECC_READ 0 |
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131 /* Reset Hardware ECC for write */ |
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132 #define NAND_ECC_WRITE 1 |
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133 /* Enable Hardware ECC before syndrom is read back from flash */ |
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134 #define NAND_ECC_READSYN 2 |
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135 |
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136 /* Bit mask for flags passed to do_nand_read_ecc */ |
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137 #define NAND_GET_DEVICE 0x80 |
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138 |
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139 |
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140 /* Option constants for bizarre disfunctionality and real |
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141 * features |
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142 */ |
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143 /* Chip can not auto increment pages */ |
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144 #define NAND_NO_AUTOINCR 0x00000001 |
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145 /* Buswitdh is 16 bit */ |
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146 #define NAND_BUSWIDTH_16 0x00000002 |
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147 /* Device supports partial programming without padding */ |
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148 #define NAND_NO_PADDING 0x00000004 |
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149 /* Chip has cache program function */ |
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150 #define NAND_CACHEPRG 0x00000008 |
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151 /* Chip has copy back function */ |
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152 #define NAND_COPYBACK 0x00000010 |
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153 /* AND Chip which has 4 banks and a confusing page / block |
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154 * assignment. See Renesas datasheet for further information */ |
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155 #define NAND_IS_AND 0x00000020 |
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156 /* Chip has a array of 4 pages which can be read without |
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157 * additional ready /busy waits */ |
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158 #define NAND_4PAGE_ARRAY 0x00000040 |
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159 /* Chip requires that BBT is periodically rewritten to prevent |
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160 * bits from adjacent blocks from 'leaking' in altering data. |
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161 * This happens with the Renesas AG-AND chips, possibly others. */ |
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162 #define BBT_AUTO_REFRESH 0x00000080 |
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163 /* Chip does not require ready check on read. True |
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164 * for all large page devices, as they do not support |
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165 * autoincrement.*/ |
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166 #define NAND_NO_READRDY 0x00000100 |
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167 /* Chip does not allow subpage writes */ |
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168 #define NAND_NO_SUBPAGE_WRITE 0x00000200 |
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169 |
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170 |
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171 /* Options valid for Samsung large page devices */ |
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172 #define NAND_SAMSUNG_LP_OPTIONS \ |
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173 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) |
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174 |
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175 /* Macros to identify the above */ |
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176 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) |
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177 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) |
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178 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
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179 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) |
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180 /* Large page NAND with SOFT_ECC should support subpage reads */ |
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181 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ |
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182 && (chip->page_shift > 9)) |
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183 |
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184 /* Mask to zero out the chip options, which come from the id table */ |
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185 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) |
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186 |
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187 /* Non chip related options */ |
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188 /* Use a flash based bad block table. This option is passed to the |
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189 * default bad block table function. */ |
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190 #define NAND_USE_FLASH_BBT 0x00010000 |
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191 /* This option skips the bbt scan during initialization. */ |
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192 #define NAND_SKIP_BBTSCAN 0x00020000 |
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193 /* This option is defined if the board driver allocates its own buffers |
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194 (e.g. because it needs them DMA-coherent */ |
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195 #define NAND_OWN_BUFFERS 0x00040000 |
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196 /* Options set by nand scan */ |
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197 /* Nand scan has allocated controller struct */ |
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198 #define NAND_CONTROLLER_ALLOC 0x80000000 |
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199 |
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200 /* Cell info constants */ |
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201 #define NAND_CI_CHIPNR_MSK 0x03 |
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202 #define NAND_CI_CELLTYPE_MSK 0x0C |
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203 |
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204 /* |
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205 * nand_state_t - chip states |
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206 * Enumeration for NAND flash chip state |
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207 */ |
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208 typedef enum { |
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209 FL_READY, |
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210 FL_READING, |
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211 FL_WRITING, |
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212 FL_ERASING, |
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213 FL_SYNCING, |
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214 FL_CACHEDPRG, |
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215 FL_PM_SUSPENDED, |
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216 } nand_state_t; |
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217 |
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218 /* Keep gcc happy */ |
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219 struct nand_chip; |
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220 |
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221 /** |
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222 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
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223 * @lock: protection lock |
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224 * @active: the mtd device which holds the controller currently |
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225 * @wq: wait queue to sleep on if a NAND operation is in progress |
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226 * used instead of the per chip wait queue when a hw controller is available |
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227 */ |
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228 struct nand_hw_control { |
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229 spinlock_t lock; |
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230 struct nand_chip *active; |
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231 wait_queue_head_t wq; |
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232 }; |
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233 |
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234 /** |
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235 * struct nand_ecc_ctrl - Control structure for ecc |
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236 * @mode: ecc mode |
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237 * @steps: number of ecc steps per page |
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238 * @size: data bytes per ecc step |
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239 * @bytes: ecc bytes per step |
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240 * @total: total number of ecc bytes per page |
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241 * @prepad: padding information for syndrome based ecc generators |
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242 * @postpad: padding information for syndrome based ecc generators |
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243 * @layout: ECC layout control struct pointer |
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244 * @hwctl: function to control hardware ecc generator. Must only |
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245 * be provided if an hardware ECC is available |
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246 * @calculate: function for ecc calculation or readback from ecc hardware |
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247 * @correct: function for ecc correction, matching to ecc generator (sw/hw) |
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248 * @read_page_raw: function to read a raw page without ECC |
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249 * @write_page_raw: function to write a raw page without ECC |
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250 * @read_page: function to read a page according to the ecc generator requirements |
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251 * @read_subpage: function to read parts of the page covered by ECC. |
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252 * @write_page: function to write a page according to the ecc generator requirements |
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253 * @read_oob: function to read chip OOB data |
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254 * @write_oob: function to write chip OOB data |
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255 */ |
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256 struct nand_ecc_ctrl { |
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257 nand_ecc_modes_t mode; |
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258 int steps; |
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259 int size; |
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260 int bytes; |
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261 int total; |
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262 int prepad; |
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263 int postpad; |
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264 struct nand_ecclayout *layout; |
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265 void (*hwctl)(struct mtd_info *mtd, int mode); |
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266 int (*calculate)(struct mtd_info *mtd, |
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267 const uint8_t *dat, |
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268 uint8_t *ecc_code); |
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269 int (*correct)(struct mtd_info *mtd, uint8_t *dat, |
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270 uint8_t *read_ecc, |
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271 uint8_t *calc_ecc); |
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272 int (*read_page_raw)(struct mtd_info *mtd, |
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273 struct nand_chip *chip, |
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274 uint8_t *buf); |
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275 void (*write_page_raw)(struct mtd_info *mtd, |
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276 struct nand_chip *chip, |
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277 const uint8_t *buf); |
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278 int (*read_page)(struct mtd_info *mtd, |
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279 struct nand_chip *chip, |
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280 uint8_t *buf); |
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281 int (*read_subpage)(struct mtd_info *mtd, |
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282 struct nand_chip *chip, |
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283 uint32_t offs, uint32_t len, |
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284 uint8_t *buf); |
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285 void (*write_page)(struct mtd_info *mtd, |
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286 struct nand_chip *chip, |
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287 const uint8_t *buf); |
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288 int (*read_oob)(struct mtd_info *mtd, |
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289 struct nand_chip *chip, |
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290 int page, |
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291 int sndcmd); |
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292 int (*write_oob)(struct mtd_info *mtd, |
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293 struct nand_chip *chip, |
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294 int page); |
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295 }; |
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296 |
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297 /** |
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298 * struct nand_buffers - buffer structure for read/write |
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299 * @ecccalc: buffer for calculated ecc |
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300 * @ecccode: buffer for ecc read from flash |
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301 * @databuf: buffer for data - dynamically sized |
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302 * |
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303 * Do not change the order of buffers. databuf and oobrbuf must be in |
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304 * consecutive order. |
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305 */ |
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306 struct nand_buffers { |
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307 uint8_t ecccalc[NAND_MAX_OOBSIZE]; |
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308 uint8_t ecccode[NAND_MAX_OOBSIZE]; |
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309 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
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310 }; |
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311 |
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312 /** |
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313 * struct nand_chip - NAND Private Flash Chip Data |
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314 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device |
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315 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device |
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316 * @read_byte: [REPLACEABLE] read one byte from the chip |
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317 * @read_word: [REPLACEABLE] read one word from the chip |
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318 * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
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319 * @read_buf: [REPLACEABLE] read data from the chip into the buffer |
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320 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data |
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321 * @select_chip: [REPLACEABLE] select chip nr |
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322 * @block_bad: [REPLACEABLE] check, if the block is bad |
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323 * @block_markbad: [REPLACEABLE] mark the block bad |
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324 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling |
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325 * ALE/CLE/nCE. Also used to write command and address |
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326 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line |
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327 * If set to NULL no access to ready/busy is available and the ready/busy information |
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328 * is read from the chip status register |
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329 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip |
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330 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready |
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331 * @ecc: [BOARDSPECIFIC] ecc control ctructure |
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332 * @buffers: buffer structure for read/write |
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333 * @hwcontrol: platform-specific hardware control structure |
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334 * @ops: oob operation operands |
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335 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support |
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336 * @scan_bbt: [REPLACEABLE] function to scan bad block table |
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337 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) |
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338 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress |
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339 * @state: [INTERN] the current state of the NAND device |
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340 * @oob_poi: poison value buffer |
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341 * @page_shift: [INTERN] number of address bits in a page (column address bits) |
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342 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
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343 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry |
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344 * @chip_shift: [INTERN] number of address bits in one chip |
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345 * @datbuf: [INTERN] internal buffer for one page + oob |
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346 * @oobbuf: [INTERN] oob buffer for one eraseblock |
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347 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized |
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348 * @data_poi: [INTERN] pointer to a data buffer |
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349 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about |
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350 * special functionality. See the defines for further explanation |
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351 * @badblockpos: [INTERN] position of the bad block marker in the oob area |
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352 * @cellinfo: [INTERN] MLC/multichip data from chip ident |
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353 * @numchips: [INTERN] number of physical chips |
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354 * @chipsize: [INTERN] the size of one chip for multichip arrays |
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355 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 |
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356 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf |
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357 * @subpagesize: [INTERN] holds the subpagesize |
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358 * @ecclayout: [REPLACEABLE] the default ecc placement scheme |
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359 * @bbt: [INTERN] bad block table pointer |
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360 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup |
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361 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
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362 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan |
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363 * @controller: [REPLACEABLE] a pointer to a hardware controller structure |
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364 * which is shared among multiple independend devices |
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365 * @priv: [OPTIONAL] pointer to private chip date |
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366 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks |
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367 * (determine if errors are correctable) |
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368 * @write_page: [REPLACEABLE] High-level page write function |
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369 */ |
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370 |
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371 struct nand_chip { |
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372 void __iomem *IO_ADDR_R; |
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373 void __iomem *IO_ADDR_W; |
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374 |
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375 uint8_t (*read_byte)(struct mtd_info *mtd); |
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376 u16 (*read_word)(struct mtd_info *mtd); |
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377 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
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378 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); |
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379 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
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380 void (*select_chip)(struct mtd_info *mtd, int chip); |
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381 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); |
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382 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); |
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383 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, |
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384 unsigned int ctrl); |
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385 int (*dev_ready)(struct mtd_info *mtd); |
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386 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); |
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387 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); |
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388 void (*erase_cmd)(struct mtd_info *mtd, int page); |
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389 int (*scan_bbt)(struct mtd_info *mtd); |
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390 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); |
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391 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
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392 const uint8_t *buf, int page, int cached, int raw); |
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393 |
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394 int chip_delay; |
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395 unsigned int options; |
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396 |
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397 int page_shift; |
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398 int phys_erase_shift; |
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399 int bbt_erase_shift; |
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400 int chip_shift; |
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401 int numchips; |
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402 unsigned long chipsize; |
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403 int pagemask; |
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404 int pagebuf; |
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405 int subpagesize; |
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406 uint8_t cellinfo; |
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407 int badblockpos; |
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408 |
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409 nand_state_t state; |
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410 |
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411 uint8_t *oob_poi; |
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412 struct nand_hw_control *controller; |
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413 struct nand_ecclayout *ecclayout; |
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414 |
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415 struct nand_ecc_ctrl ecc; |
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416 struct nand_buffers *buffers; |
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417 struct nand_hw_control hwcontrol; |
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418 |
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419 struct mtd_oob_ops ops; |
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420 |
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421 uint8_t *bbt; |
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422 struct nand_bbt_descr *bbt_td; |
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423 struct nand_bbt_descr *bbt_md; |
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424 |
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425 struct nand_bbt_descr *badblock_pattern; |
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426 |
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427 void *priv; |
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428 }; |
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429 |
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430 /* |
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431 * NAND Flash Manufacturer ID Codes |
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432 */ |
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433 #define NAND_MFR_TOSHIBA 0x98 |
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434 #define NAND_MFR_SAMSUNG 0xec |
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435 #define NAND_MFR_FUJITSU 0x04 |
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436 #define NAND_MFR_NATIONAL 0x8f |
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437 #define NAND_MFR_RENESAS 0x07 |
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438 #define NAND_MFR_STMICRO 0x20 |
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439 #define NAND_MFR_HYNIX 0xad |
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440 #define NAND_MFR_MICRON 0x2c |
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441 #define NAND_MFR_AMD 0x01 |
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442 |
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443 /** |
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444 * struct nand_flash_dev - NAND Flash Device ID Structure |
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445 * @name: Identify the device type |
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446 * @id: device ID code |
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447 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 |
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448 * If the pagesize is 0, then the real pagesize |
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449 * and the eraseize are determined from the |
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450 * extended id bytes in the chip |
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451 * @erasesize: Size of an erase block in the flash device. |
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452 * @chipsize: Total chipsize in Mega Bytes |
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453 * @options: Bitfield to store chip relevant options |
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454 */ |
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455 struct nand_flash_dev { |
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456 char *name; |
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457 int id; |
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458 unsigned long pagesize; |
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459 unsigned long chipsize; |
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460 unsigned long erasesize; |
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461 unsigned long options; |
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462 }; |
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463 |
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464 /** |
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465 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure |
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466 * @name: Manufacturer name |
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467 * @id: manufacturer ID code of device. |
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468 */ |
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469 struct nand_manufacturers { |
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470 int id; |
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471 char * name; |
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472 }; |
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473 |
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474 extern struct nand_flash_dev nand_flash_ids[]; |
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475 extern struct nand_manufacturers nand_manuf_ids[]; |
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476 |
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477 /** |
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478 * struct nand_bbt_descr - bad block table descriptor |
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479 * @options: options for this descriptor |
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480 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE |
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481 * when bbt is searched, then we store the found bbts pages here. |
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482 * Its an array and supports up to 8 chips now |
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483 * @offs: offset of the pattern in the oob area of the page |
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484 * @veroffs: offset of the bbt version counter in the oob are of the page |
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485 * @version: version read from the bbt page during scan |
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486 * @len: length of the pattern, if 0 no pattern check is performed |
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487 * @maxblocks: maximum number of blocks to search for a bbt. This number of |
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488 * blocks is reserved at the end of the device where the tables are |
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489 * written. |
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490 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than |
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491 * bad) block in the stored bbt |
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492 * @pattern: pattern to identify bad block table or factory marked good / |
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493 * bad blocks, can be NULL, if len = 0 |
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494 * |
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495 * Descriptor for the bad block table marker and the descriptor for the |
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496 * pattern which identifies good and bad blocks. The assumption is made |
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497 * that the pattern and the version count are always located in the oob area |
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498 * of the first block. |
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499 */ |
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500 struct nand_bbt_descr { |
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501 int options; |
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502 int pages[NAND_MAX_CHIPS]; |
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503 int offs; |
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504 int veroffs; |
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505 uint8_t version[NAND_MAX_CHIPS]; |
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506 int len; |
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507 int maxblocks; |
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508 int reserved_block_code; |
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509 uint8_t *pattern; |
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510 }; |
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511 |
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512 /* Options for the bad block table descriptors */ |
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513 |
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514 /* The number of bits used per block in the bbt on the device */ |
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515 #define NAND_BBT_NRBITS_MSK 0x0000000F |
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516 #define NAND_BBT_1BIT 0x00000001 |
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517 #define NAND_BBT_2BIT 0x00000002 |
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518 #define NAND_BBT_4BIT 0x00000004 |
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519 #define NAND_BBT_8BIT 0x00000008 |
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520 /* The bad block table is in the last good block of the device */ |
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521 #define NAND_BBT_LASTBLOCK 0x00000010 |
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522 /* The bbt is at the given page, else we must scan for the bbt */ |
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523 #define NAND_BBT_ABSPAGE 0x00000020 |
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524 /* The bbt is at the given page, else we must scan for the bbt */ |
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525 #define NAND_BBT_SEARCH 0x00000040 |
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526 /* bbt is stored per chip on multichip devices */ |
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527 #define NAND_BBT_PERCHIP 0x00000080 |
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528 /* bbt has a version counter at offset veroffs */ |
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529 #define NAND_BBT_VERSION 0x00000100 |
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530 /* Create a bbt if none axists */ |
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531 #define NAND_BBT_CREATE 0x00000200 |
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532 /* Search good / bad pattern through all pages of a block */ |
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533 #define NAND_BBT_SCANALLPAGES 0x00000400 |
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534 /* Scan block empty during good / bad block scan */ |
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535 #define NAND_BBT_SCANEMPTY 0x00000800 |
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536 /* Write bbt if neccecary */ |
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537 #define NAND_BBT_WRITE 0x00001000 |
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538 /* Read and write back block contents when writing bbt */ |
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539 #define NAND_BBT_SAVECONTENT 0x00002000 |
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540 /* Search good / bad pattern on the first and the second page */ |
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541 #define NAND_BBT_SCAN2NDPAGE 0x00004000 |
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542 |
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543 /* The maximum number of blocks to scan for a bbt */ |
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544 #define NAND_BBT_SCAN_MAXBLOCKS 4 |
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545 |
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546 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
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547 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); |
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548 extern int nand_default_bbt(struct mtd_info *mtd); |
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549 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); |
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550 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
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551 int allowbbt); |
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552 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, |
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553 size_t * retlen, uint8_t * buf); |
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554 |
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555 /* |
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556 * Constants for oob configuration |
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557 */ |
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558 #define NAND_SMALL_BADBLOCK_POS 5 |
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559 #define NAND_LARGE_BADBLOCK_POS 0 |
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560 |
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561 /** |
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562 * struct platform_nand_chip - chip level device structure |
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563 * @nr_chips: max. number of chips to scan for |
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564 * @chip_offset: chip number offset |
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565 * @nr_partitions: number of partitions pointed to by partitions (or zero) |
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566 * @partitions: mtd partition list |
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567 * @chip_delay: R/B delay value in us |
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568 * @options: Option flags, e.g. 16bit buswidth |
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569 * @ecclayout: ecc layout info structure |
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570 * @part_probe_types: NULL-terminated array of probe types |
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571 * @priv: hardware controller specific settings |
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572 */ |
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573 struct platform_nand_chip { |
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574 int nr_chips; |
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575 int chip_offset; |
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576 int nr_partitions; |
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577 struct mtd_partition *partitions; |
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578 struct nand_ecclayout *ecclayout; |
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579 int chip_delay; |
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580 unsigned int options; |
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581 const char **part_probe_types; |
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582 void *priv; |
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583 }; |
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584 |
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585 /** |
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586 * struct platform_nand_ctrl - controller level device structure |
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587 * @hwcontrol: platform specific hardware control structure |
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588 * @dev_ready: platform specific function to read ready/busy pin |
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589 * @select_chip: platform specific chip select function |
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590 * @cmd_ctrl: platform specific function for controlling |
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591 * ALE/CLE/nCE. Also used to write command and address |
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592 * @priv: private data to transport driver specific settings |
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593 * |
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594 * All fields are optional and depend on the hardware driver requirements |
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595 */ |
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596 struct platform_nand_ctrl { |
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597 void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
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598 int (*dev_ready)(struct mtd_info *mtd); |
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599 void (*select_chip)(struct mtd_info *mtd, int chip); |
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600 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, |
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601 unsigned int ctrl); |
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602 void *priv; |
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603 }; |
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604 |
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605 /** |
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606 * struct platform_nand_data - container structure for platform-specific data |
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607 * @chip: chip level chip structure |
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608 * @ctrl: controller level device structure |
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609 */ |
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610 struct platform_nand_data { |
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611 struct platform_nand_chip chip; |
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612 struct platform_nand_ctrl ctrl; |
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613 }; |
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614 |
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615 /* Some helpers to access the data structures */ |
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616 static inline |
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617 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) |
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618 { |
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619 struct nand_chip *chip = mtd->priv; |
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620 |
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621 return chip->priv; |
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622 } |
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623 |
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624 #endif /* __LINUX_MTD_NAND_H */ |