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1 |
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2 /* Common Flash Interface structures |
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3 * See http://support.intel.com/design/flash/technote/index.htm |
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4 */ |
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5 |
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6 #ifndef __MTD_CFI_H__ |
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7 #define __MTD_CFI_H__ |
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8 |
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9 #include <linux/delay.h> |
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10 #include <linux/types.h> |
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11 #include <linux/interrupt.h> |
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12 #include <linux/mtd/flashchip.h> |
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13 #include <linux/mtd/map.h> |
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14 #include <linux/mtd/cfi_endian.h> |
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15 #include <linux/mtd/xip.h> |
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16 |
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17 #ifdef CONFIG_MTD_CFI_I1 |
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18 #define cfi_interleave(cfi) 1 |
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19 #define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1) |
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20 #else |
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21 #define cfi_interleave_is_1(cfi) (0) |
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22 #endif |
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23 |
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24 #ifdef CONFIG_MTD_CFI_I2 |
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25 # ifdef cfi_interleave |
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26 # undef cfi_interleave |
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27 # define cfi_interleave(cfi) ((cfi)->interleave) |
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28 # else |
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29 # define cfi_interleave(cfi) 2 |
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30 # endif |
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31 #define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2) |
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32 #else |
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33 #define cfi_interleave_is_2(cfi) (0) |
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34 #endif |
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35 |
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36 #ifdef CONFIG_MTD_CFI_I4 |
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37 # ifdef cfi_interleave |
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38 # undef cfi_interleave |
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39 # define cfi_interleave(cfi) ((cfi)->interleave) |
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40 # else |
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41 # define cfi_interleave(cfi) 4 |
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42 # endif |
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43 #define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4) |
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44 #else |
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45 #define cfi_interleave_is_4(cfi) (0) |
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46 #endif |
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47 |
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48 #ifdef CONFIG_MTD_CFI_I8 |
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49 # ifdef cfi_interleave |
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50 # undef cfi_interleave |
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51 # define cfi_interleave(cfi) ((cfi)->interleave) |
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52 # else |
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53 # define cfi_interleave(cfi) 8 |
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54 # endif |
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55 #define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8) |
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56 #else |
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57 #define cfi_interleave_is_8(cfi) (0) |
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58 #endif |
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59 |
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60 #ifndef cfi_interleave |
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61 #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. |
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62 static inline int cfi_interleave(void *cfi) |
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63 { |
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64 BUG(); |
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65 return 0; |
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66 } |
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67 #endif |
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68 |
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69 static inline int cfi_interleave_supported(int i) |
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70 { |
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71 switch (i) { |
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72 #ifdef CONFIG_MTD_CFI_I1 |
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73 case 1: |
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74 #endif |
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75 #ifdef CONFIG_MTD_CFI_I2 |
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76 case 2: |
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77 #endif |
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78 #ifdef CONFIG_MTD_CFI_I4 |
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79 case 4: |
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80 #endif |
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81 #ifdef CONFIG_MTD_CFI_I8 |
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82 case 8: |
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83 #endif |
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84 return 1; |
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85 |
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86 default: |
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87 return 0; |
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88 } |
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89 } |
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90 |
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91 |
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92 /* NB: these values must represents the number of bytes needed to meet the |
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93 * device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes. |
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94 * These numbers are used in calculations. |
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95 */ |
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96 #define CFI_DEVICETYPE_X8 (8 / 8) |
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97 #define CFI_DEVICETYPE_X16 (16 / 8) |
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98 #define CFI_DEVICETYPE_X32 (32 / 8) |
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99 #define CFI_DEVICETYPE_X64 (64 / 8) |
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100 |
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101 |
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102 /* Device Interface Code Assignments from the "Common Flash Memory Interface |
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103 * Publication 100" dated December 1, 2001. |
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104 */ |
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105 #define CFI_INTERFACE_X8_ASYNC 0x0000 |
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106 #define CFI_INTERFACE_X16_ASYNC 0x0001 |
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107 #define CFI_INTERFACE_X8_BY_X16_ASYNC 0x0002 |
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108 #define CFI_INTERFACE_X32_ASYNC 0x0003 |
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109 #define CFI_INTERFACE_X16_BY_X32_ASYNC 0x0005 |
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110 #define CFI_INTERFACE_NOT_ALLOWED 0xffff |
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111 |
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112 |
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113 /* NB: We keep these structures in memory in HOST byteorder, except |
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114 * where individually noted. |
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115 */ |
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116 |
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117 /* Basic Query Structure */ |
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118 struct cfi_ident { |
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119 uint8_t qry[3]; |
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120 uint16_t P_ID; |
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121 uint16_t P_ADR; |
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122 uint16_t A_ID; |
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123 uint16_t A_ADR; |
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124 uint8_t VccMin; |
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125 uint8_t VccMax; |
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126 uint8_t VppMin; |
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127 uint8_t VppMax; |
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128 uint8_t WordWriteTimeoutTyp; |
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129 uint8_t BufWriteTimeoutTyp; |
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130 uint8_t BlockEraseTimeoutTyp; |
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131 uint8_t ChipEraseTimeoutTyp; |
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132 uint8_t WordWriteTimeoutMax; |
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133 uint8_t BufWriteTimeoutMax; |
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134 uint8_t BlockEraseTimeoutMax; |
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135 uint8_t ChipEraseTimeoutMax; |
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136 uint8_t DevSize; |
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137 uint16_t InterfaceDesc; |
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138 uint16_t MaxBufWriteSize; |
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139 uint8_t NumEraseRegions; |
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140 uint32_t EraseRegionInfo[0]; /* Not host ordered */ |
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141 } __attribute__((packed)); |
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142 |
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143 /* Extended Query Structure for both PRI and ALT */ |
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144 |
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145 struct cfi_extquery { |
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146 uint8_t pri[3]; |
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147 uint8_t MajorVersion; |
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148 uint8_t MinorVersion; |
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149 } __attribute__((packed)); |
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150 |
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151 /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */ |
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152 |
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153 struct cfi_pri_intelext { |
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154 uint8_t pri[3]; |
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155 uint8_t MajorVersion; |
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156 uint8_t MinorVersion; |
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157 uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature |
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158 block follows - FIXME - not currently supported */ |
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159 uint8_t SuspendCmdSupport; |
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160 uint16_t BlkStatusRegMask; |
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161 uint8_t VccOptimal; |
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162 uint8_t VppOptimal; |
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163 uint8_t NumProtectionFields; |
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164 uint16_t ProtRegAddr; |
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165 uint8_t FactProtRegSize; |
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166 uint8_t UserProtRegSize; |
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167 uint8_t extra[0]; |
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168 } __attribute__((packed)); |
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169 |
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170 struct cfi_intelext_otpinfo { |
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171 uint32_t ProtRegAddr; |
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172 uint16_t FactGroups; |
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173 uint8_t FactProtRegSize; |
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174 uint16_t UserGroups; |
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175 uint8_t UserProtRegSize; |
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176 } __attribute__((packed)); |
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177 |
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178 struct cfi_intelext_blockinfo { |
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179 uint16_t NumIdentBlocks; |
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180 uint16_t BlockSize; |
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181 uint16_t MinBlockEraseCycles; |
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182 uint8_t BitsPerCell; |
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183 uint8_t BlockCap; |
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184 } __attribute__((packed)); |
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185 |
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186 struct cfi_intelext_regioninfo { |
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187 uint16_t NumIdentPartitions; |
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188 uint8_t NumOpAllowed; |
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189 uint8_t NumOpAllowedSimProgMode; |
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190 uint8_t NumOpAllowedSimEraMode; |
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191 uint8_t NumBlockTypes; |
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192 struct cfi_intelext_blockinfo BlockTypes[1]; |
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193 } __attribute__((packed)); |
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194 |
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195 struct cfi_intelext_programming_regioninfo { |
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196 uint8_t ProgRegShift; |
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197 uint8_t Reserved1; |
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198 uint8_t ControlValid; |
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199 uint8_t Reserved2; |
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200 uint8_t ControlInvalid; |
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201 uint8_t Reserved3; |
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202 } __attribute__((packed)); |
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203 |
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204 /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */ |
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205 |
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206 struct cfi_pri_amdstd { |
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207 uint8_t pri[3]; |
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208 uint8_t MajorVersion; |
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209 uint8_t MinorVersion; |
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210 uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */ |
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211 uint8_t EraseSuspend; |
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212 uint8_t BlkProt; |
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213 uint8_t TmpBlkUnprotect; |
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214 uint8_t BlkProtUnprot; |
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215 uint8_t SimultaneousOps; |
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216 uint8_t BurstMode; |
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217 uint8_t PageMode; |
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218 uint8_t VppMin; |
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219 uint8_t VppMax; |
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220 uint8_t TopBottom; |
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221 } __attribute__((packed)); |
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222 |
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223 /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */ |
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224 |
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225 struct cfi_pri_atmel { |
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226 uint8_t pri[3]; |
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227 uint8_t MajorVersion; |
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228 uint8_t MinorVersion; |
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229 uint8_t Features; |
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230 uint8_t BottomBoot; |
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231 uint8_t BurstMode; |
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232 uint8_t PageMode; |
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233 } __attribute__((packed)); |
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234 |
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235 struct cfi_pri_query { |
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236 uint8_t NumFields; |
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237 uint32_t ProtField[1]; /* Not host ordered */ |
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238 } __attribute__((packed)); |
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239 |
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240 struct cfi_bri_query { |
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241 uint8_t PageModeReadCap; |
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242 uint8_t NumFields; |
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243 uint32_t ConfField[1]; /* Not host ordered */ |
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244 } __attribute__((packed)); |
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245 |
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246 #define P_ID_NONE 0x0000 |
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247 #define P_ID_INTEL_EXT 0x0001 |
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248 #define P_ID_AMD_STD 0x0002 |
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249 #define P_ID_INTEL_STD 0x0003 |
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250 #define P_ID_AMD_EXT 0x0004 |
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251 #define P_ID_WINBOND 0x0006 |
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252 #define P_ID_ST_ADV 0x0020 |
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253 #define P_ID_MITSUBISHI_STD 0x0100 |
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254 #define P_ID_MITSUBISHI_EXT 0x0101 |
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255 #define P_ID_SST_PAGE 0x0102 |
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256 #define P_ID_INTEL_PERFORMANCE 0x0200 |
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257 #define P_ID_INTEL_DATA 0x0210 |
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258 #define P_ID_RESERVED 0xffff |
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259 |
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260 |
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261 #define CFI_MODE_CFI 1 |
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262 #define CFI_MODE_JEDEC 0 |
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263 |
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264 struct cfi_private { |
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265 uint16_t cmdset; |
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266 void *cmdset_priv; |
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267 int interleave; |
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268 int device_type; |
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269 int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */ |
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270 int addr_unlock1; |
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271 int addr_unlock2; |
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272 struct mtd_info *(*cmdset_setup)(struct map_info *); |
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273 struct cfi_ident *cfiq; /* For now only one. We insist that all devs |
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274 must be of the same type. */ |
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275 int mfr, id; |
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276 int numchips; |
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277 unsigned long chipshift; /* Because they're of the same type */ |
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278 const char *im_name; /* inter_module name for cmdset_setup */ |
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279 struct flchip chips[0]; /* per-chip data structure for each chip */ |
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280 }; |
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281 |
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282 /* |
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283 * Returns the command address according to the given geometry. |
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284 */ |
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285 static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, |
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286 struct map_info *map, struct cfi_private *cfi) |
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287 { |
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288 unsigned bankwidth = map_bankwidth(map); |
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289 unsigned interleave = cfi_interleave(cfi); |
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290 unsigned type = cfi->device_type; |
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291 uint32_t addr; |
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292 |
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293 addr = (cmd_ofs * type) * interleave; |
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294 |
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295 /* Modify the unlock address if we are in compatiblity mode. |
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296 * For 16bit devices on 8 bit busses |
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297 * and 32bit devices on 16 bit busses |
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298 * set the low bit of the alternating bit sequence of the address. |
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299 */ |
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300 if (((type * interleave) > bankwidth) && ((uint8_t)cmd_ofs == 0xaa)) |
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301 addr |= (type >> 1)*interleave; |
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302 |
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303 return addr; |
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304 } |
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305 |
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306 /* |
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307 * Transforms the CFI command for the given geometry (bus width & interleave). |
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308 * It looks too long to be inline, but in the common case it should almost all |
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309 * get optimised away. |
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310 */ |
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311 static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi) |
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312 { |
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313 map_word val = { {0} }; |
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314 int wordwidth, words_per_bus, chip_mode, chips_per_word; |
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315 unsigned long onecmd; |
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316 int i; |
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317 |
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318 /* We do it this way to give the compiler a fighting chance |
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319 of optimising away all the crap for 'bankwidth' larger than |
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320 an unsigned long, in the common case where that support is |
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321 disabled */ |
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322 if (map_bankwidth_is_large(map)) { |
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323 wordwidth = sizeof(unsigned long); |
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324 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1 |
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325 } else { |
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326 wordwidth = map_bankwidth(map); |
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327 words_per_bus = 1; |
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328 } |
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329 |
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330 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); |
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331 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); |
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332 |
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333 /* First, determine what the bit-pattern should be for a single |
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334 device, according to chip mode and endianness... */ |
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335 switch (chip_mode) { |
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336 default: BUG(); |
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337 case 1: |
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338 onecmd = cmd; |
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339 break; |
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340 case 2: |
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341 onecmd = cpu_to_cfi16(cmd); |
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342 break; |
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343 case 4: |
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344 onecmd = cpu_to_cfi32(cmd); |
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345 break; |
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346 } |
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347 |
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348 /* Now replicate it across the size of an unsigned long, or |
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349 just to the bus width as appropriate */ |
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350 switch (chips_per_word) { |
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351 default: BUG(); |
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352 #if BITS_PER_LONG >= 64 |
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353 case 8: |
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354 onecmd |= (onecmd << (chip_mode * 32)); |
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355 #endif |
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356 case 4: |
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357 onecmd |= (onecmd << (chip_mode * 16)); |
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358 case 2: |
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359 onecmd |= (onecmd << (chip_mode * 8)); |
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360 case 1: |
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361 ; |
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362 } |
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363 |
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364 /* And finally, for the multi-word case, replicate it |
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365 in all words in the structure */ |
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366 for (i=0; i < words_per_bus; i++) { |
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367 val.x[i] = onecmd; |
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368 } |
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369 |
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370 return val; |
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371 } |
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372 #define CMD(x) cfi_build_cmd((x), map, cfi) |
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373 |
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374 |
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375 static inline unsigned long cfi_merge_status(map_word val, struct map_info *map, |
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376 struct cfi_private *cfi) |
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377 { |
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378 int wordwidth, words_per_bus, chip_mode, chips_per_word; |
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379 unsigned long onestat, res = 0; |
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380 int i; |
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381 |
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382 /* We do it this way to give the compiler a fighting chance |
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383 of optimising away all the crap for 'bankwidth' larger than |
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384 an unsigned long, in the common case where that support is |
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385 disabled */ |
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386 if (map_bankwidth_is_large(map)) { |
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387 wordwidth = sizeof(unsigned long); |
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388 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1 |
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389 } else { |
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390 wordwidth = map_bankwidth(map); |
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391 words_per_bus = 1; |
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392 } |
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393 |
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394 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); |
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395 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); |
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396 |
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397 onestat = val.x[0]; |
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398 /* Or all status words together */ |
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399 for (i=1; i < words_per_bus; i++) { |
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400 onestat |= val.x[i]; |
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401 } |
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402 |
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403 res = onestat; |
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404 switch(chips_per_word) { |
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405 default: BUG(); |
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406 #if BITS_PER_LONG >= 64 |
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407 case 8: |
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408 res |= (onestat >> (chip_mode * 32)); |
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409 #endif |
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410 case 4: |
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411 res |= (onestat >> (chip_mode * 16)); |
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412 case 2: |
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413 res |= (onestat >> (chip_mode * 8)); |
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414 case 1: |
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415 ; |
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416 } |
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417 |
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418 /* Last, determine what the bit-pattern should be for a single |
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419 device, according to chip mode and endianness... */ |
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420 switch (chip_mode) { |
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421 case 1: |
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422 break; |
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423 case 2: |
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424 res = cfi16_to_cpu(res); |
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425 break; |
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426 case 4: |
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427 res = cfi32_to_cpu(res); |
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428 break; |
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429 default: BUG(); |
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430 } |
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431 return res; |
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432 } |
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433 |
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434 #define MERGESTATUS(x) cfi_merge_status((x), map, cfi) |
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435 |
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436 |
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437 /* |
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438 * Sends a CFI command to a bank of flash for the given geometry. |
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439 * |
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440 * Returns the offset in flash where the command was written. |
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441 * If prev_val is non-null, it will be set to the value at the command address, |
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442 * before the command was written. |
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443 */ |
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444 static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base, |
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445 struct map_info *map, struct cfi_private *cfi, |
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446 int type, map_word *prev_val) |
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447 { |
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448 map_word val; |
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449 uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi); |
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450 val = cfi_build_cmd(cmd, map, cfi); |
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451 |
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452 if (prev_val) |
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453 *prev_val = map_read(map, addr); |
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454 |
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455 map_write(map, val, addr); |
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456 |
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457 return addr - base; |
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458 } |
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459 |
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460 static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr) |
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461 { |
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462 map_word val = map_read(map, addr); |
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463 |
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464 if (map_bankwidth_is_1(map)) { |
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465 return val.x[0]; |
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466 } else if (map_bankwidth_is_2(map)) { |
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467 return cfi16_to_cpu(val.x[0]); |
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468 } else { |
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469 /* No point in a 64-bit byteswap since that would just be |
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470 swapping the responses from different chips, and we are |
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471 only interested in one chip (a representative sample) */ |
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472 return cfi32_to_cpu(val.x[0]); |
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473 } |
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474 } |
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475 |
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476 static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr) |
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477 { |
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478 map_word val = map_read(map, addr); |
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479 |
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480 if (map_bankwidth_is_1(map)) { |
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481 return val.x[0] & 0xff; |
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482 } else if (map_bankwidth_is_2(map)) { |
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483 return cfi16_to_cpu(val.x[0]); |
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484 } else { |
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485 /* No point in a 64-bit byteswap since that would just be |
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486 swapping the responses from different chips, and we are |
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487 only interested in one chip (a representative sample) */ |
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488 return cfi32_to_cpu(val.x[0]); |
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489 } |
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490 } |
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491 |
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492 static inline void cfi_udelay(int us) |
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493 { |
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494 if (us >= 1000) { |
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495 msleep((us+999)/1000); |
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496 } else { |
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497 udelay(us); |
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498 cond_resched(); |
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499 } |
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500 } |
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501 |
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502 int __xipram cfi_qry_present(struct map_info *map, __u32 base, |
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503 struct cfi_private *cfi); |
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504 int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map, |
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505 struct cfi_private *cfi); |
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506 void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map, |
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507 struct cfi_private *cfi); |
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508 |
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509 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size, |
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510 const char* name); |
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511 struct cfi_fixup { |
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512 uint16_t mfr; |
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513 uint16_t id; |
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514 void (*fixup)(struct mtd_info *mtd, void* param); |
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515 void* param; |
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516 }; |
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517 |
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518 #define CFI_MFR_ANY 0xffff |
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519 #define CFI_ID_ANY 0xffff |
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520 |
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521 #define CFI_MFR_AMD 0x0001 |
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522 #define CFI_MFR_ATMEL 0x001F |
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523 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ |
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524 |
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525 void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups); |
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526 |
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527 typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip, |
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528 unsigned long adr, int len, void *thunk); |
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529 |
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530 int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob, |
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531 loff_t ofs, size_t len, void *thunk); |
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532 |
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533 |
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534 #endif /* __MTD_CFI_H__ */ |