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1 /* |
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2 * wm8400 private definitions. |
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3 * |
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4 * Copyright 2008 Wolfson Microelectronics plc |
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5 * |
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6 * This program is free software; you can redistribute it and/or modify |
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7 * it under the terms of the GNU General Public License as published by |
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8 * the Free Software Foundation; either version 2 of the License, or |
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9 * (at your option) any later version. |
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10 * |
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11 * This program is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 * GNU General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU General Public License |
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17 * along with this program; if not, write to the Free Software |
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18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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19 */ |
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20 |
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21 #ifndef __LINUX_MFD_WM8400_PRIV_H |
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22 #define __LINUX_MFD_WM8400_PRIV_H |
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23 |
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24 #include <linux/mfd/wm8400.h> |
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25 #include <linux/mutex.h> |
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26 #include <linux/platform_device.h> |
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27 |
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28 #define WM8400_REGISTER_COUNT 0x55 |
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29 |
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30 struct wm8400 { |
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31 struct device *dev; |
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32 |
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33 int (*read_dev)(void *data, char reg, int count, u16 *dst); |
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34 int (*write_dev)(void *data, char reg, int count, const u16 *src); |
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35 |
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36 struct mutex io_lock; |
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37 void *io_data; |
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38 |
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39 u16 reg_cache[WM8400_REGISTER_COUNT]; |
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40 |
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41 struct platform_device regulators[6]; |
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42 }; |
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43 |
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44 /* |
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45 * Register values. |
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46 */ |
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47 #define WM8400_RESET_ID 0x00 |
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48 #define WM8400_ID 0x01 |
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49 #define WM8400_POWER_MANAGEMENT_1 0x02 |
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50 #define WM8400_POWER_MANAGEMENT_2 0x03 |
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51 #define WM8400_POWER_MANAGEMENT_3 0x04 |
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52 #define WM8400_AUDIO_INTERFACE_1 0x05 |
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53 #define WM8400_AUDIO_INTERFACE_2 0x06 |
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54 #define WM8400_CLOCKING_1 0x07 |
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55 #define WM8400_CLOCKING_2 0x08 |
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56 #define WM8400_AUDIO_INTERFACE_3 0x09 |
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57 #define WM8400_AUDIO_INTERFACE_4 0x0A |
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58 #define WM8400_DAC_CTRL 0x0B |
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59 #define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C |
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60 #define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D |
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61 #define WM8400_DIGITAL_SIDE_TONE 0x0E |
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62 #define WM8400_ADC_CTRL 0x0F |
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63 #define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10 |
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64 #define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11 |
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65 #define WM8400_GPIO_CTRL_1 0x12 |
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66 #define WM8400_GPIO1_GPIO2 0x13 |
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67 #define WM8400_GPIO3_GPIO4 0x14 |
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68 #define WM8400_GPIO5_GPIO6 0x15 |
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69 #define WM8400_GPIOCTRL_2 0x16 |
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70 #define WM8400_GPIO_POL 0x17 |
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71 #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18 |
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72 #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19 |
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73 #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A |
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74 #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B |
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75 #define WM8400_LEFT_OUTPUT_VOLUME 0x1C |
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76 #define WM8400_RIGHT_OUTPUT_VOLUME 0x1D |
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77 #define WM8400_LINE_OUTPUTS_VOLUME 0x1E |
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78 #define WM8400_OUT3_4_VOLUME 0x1F |
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79 #define WM8400_LEFT_OPGA_VOLUME 0x20 |
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80 #define WM8400_RIGHT_OPGA_VOLUME 0x21 |
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81 #define WM8400_SPEAKER_VOLUME 0x22 |
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82 #define WM8400_CLASSD1 0x23 |
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83 #define WM8400_CLASSD3 0x25 |
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84 #define WM8400_INPUT_MIXER1 0x27 |
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85 #define WM8400_INPUT_MIXER2 0x28 |
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86 #define WM8400_INPUT_MIXER3 0x29 |
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87 #define WM8400_INPUT_MIXER4 0x2A |
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88 #define WM8400_INPUT_MIXER5 0x2B |
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89 #define WM8400_INPUT_MIXER6 0x2C |
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90 #define WM8400_OUTPUT_MIXER1 0x2D |
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91 #define WM8400_OUTPUT_MIXER2 0x2E |
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92 #define WM8400_OUTPUT_MIXER3 0x2F |
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93 #define WM8400_OUTPUT_MIXER4 0x30 |
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94 #define WM8400_OUTPUT_MIXER5 0x31 |
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95 #define WM8400_OUTPUT_MIXER6 0x32 |
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96 #define WM8400_OUT3_4_MIXER 0x33 |
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97 #define WM8400_LINE_MIXER1 0x34 |
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98 #define WM8400_LINE_MIXER2 0x35 |
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99 #define WM8400_SPEAKER_MIXER 0x36 |
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100 #define WM8400_ADDITIONAL_CONTROL 0x37 |
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101 #define WM8400_ANTIPOP1 0x38 |
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102 #define WM8400_ANTIPOP2 0x39 |
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103 #define WM8400_MICBIAS 0x3A |
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104 #define WM8400_FLL_CONTROL_1 0x3C |
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105 #define WM8400_FLL_CONTROL_2 0x3D |
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106 #define WM8400_FLL_CONTROL_3 0x3E |
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107 #define WM8400_FLL_CONTROL_4 0x3F |
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108 #define WM8400_LDO1_CONTROL 0x41 |
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109 #define WM8400_LDO2_CONTROL 0x42 |
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110 #define WM8400_LDO3_CONTROL 0x43 |
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111 #define WM8400_LDO4_CONTROL 0x44 |
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112 #define WM8400_DCDC1_CONTROL_1 0x46 |
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113 #define WM8400_DCDC1_CONTROL_2 0x47 |
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114 #define WM8400_DCDC2_CONTROL_1 0x48 |
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115 #define WM8400_DCDC2_CONTROL_2 0x49 |
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116 #define WM8400_INTERFACE 0x4B |
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117 #define WM8400_PM_GENERAL 0x4C |
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118 #define WM8400_PM_SHUTDOWN_CONTROL 0x4E |
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119 #define WM8400_INTERRUPT_STATUS_1 0x4F |
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120 #define WM8400_INTERRUPT_STATUS_1_MASK 0x50 |
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121 #define WM8400_INTERRUPT_LEVELS 0x51 |
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122 #define WM8400_SHUTDOWN_REASON 0x52 |
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123 #define WM8400_LINE_CIRCUITS 0x54 |
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124 |
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125 /* |
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126 * Field Definitions. |
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127 */ |
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128 |
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129 /* |
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130 * R0 (0x00) - Reset/ID |
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131 */ |
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132 #define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */ |
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133 #define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */ |
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134 #define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */ |
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135 |
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136 /* |
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137 * R1 (0x01) - ID |
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138 */ |
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139 #define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */ |
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140 #define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */ |
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141 #define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */ |
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142 |
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143 /* |
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144 * R18 (0x12) - GPIO CTRL 1 |
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145 */ |
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146 #define WM8400_IRQ 0x1000 /* IRQ */ |
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147 #define WM8400_IRQ_MASK 0x1000 /* IRQ */ |
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148 #define WM8400_IRQ_SHIFT 12 /* IRQ */ |
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149 #define WM8400_IRQ_WIDTH 1 /* IRQ */ |
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150 #define WM8400_TEMPOK 0x0800 /* TEMPOK */ |
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151 #define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */ |
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152 #define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */ |
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153 #define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */ |
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154 #define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */ |
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155 #define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */ |
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156 #define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */ |
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157 #define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */ |
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158 #define WM8400_MIC1DET 0x0200 /* MIC1DET */ |
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159 #define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */ |
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160 #define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */ |
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161 #define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */ |
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162 #define WM8400_FLL_LCK 0x0100 /* FLL_LCK */ |
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163 #define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */ |
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164 #define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */ |
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165 #define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */ |
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166 #define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */ |
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167 #define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */ |
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168 #define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */ |
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169 |
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170 /* |
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171 * R19 (0x13) - GPIO1 & GPIO2 |
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172 */ |
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173 #define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ |
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174 #define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */ |
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175 #define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */ |
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176 #define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */ |
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177 #define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ |
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178 #define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */ |
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179 #define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */ |
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180 #define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */ |
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181 #define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */ |
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182 #define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */ |
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183 #define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */ |
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184 #define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ |
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185 #define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */ |
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186 #define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */ |
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187 #define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */ |
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188 #define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ |
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189 #define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ |
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190 #define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */ |
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191 #define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */ |
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192 #define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ |
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193 #define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */ |
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194 #define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */ |
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195 #define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */ |
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196 #define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ |
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197 #define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */ |
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198 #define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */ |
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199 #define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */ |
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200 #define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */ |
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201 #define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ |
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202 #define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ |
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203 #define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ |
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204 #define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */ |
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205 #define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ |
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206 #define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ |
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207 #define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ |
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208 #define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ |
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209 #define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ |
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210 #define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ |
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211 |
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212 /* |
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213 * R20 (0x14) - GPIO3 & GPIO4 |
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214 */ |
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215 #define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ |
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216 #define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */ |
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217 #define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */ |
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218 #define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */ |
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219 #define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ |
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220 #define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */ |
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221 #define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */ |
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222 #define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */ |
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223 #define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */ |
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224 #define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */ |
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225 #define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */ |
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226 #define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */ |
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227 #define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */ |
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228 #define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */ |
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229 #define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */ |
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230 #define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */ |
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231 #define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ |
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232 #define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */ |
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233 #define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */ |
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234 #define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ |
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235 #define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */ |
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236 #define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */ |
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237 #define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */ |
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238 #define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ |
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239 #define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */ |
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240 #define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */ |
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241 #define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */ |
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242 #define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */ |
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243 #define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ |
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244 #define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ |
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245 #define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ |
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246 #define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */ |
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247 #define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ |
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248 #define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ |
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249 #define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ |
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250 #define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ |
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251 #define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ |
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252 #define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ |
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253 |
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254 /* |
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255 * R21 (0x15) - GPIO5 & GPIO6 |
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256 */ |
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257 #define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ |
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258 #define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */ |
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259 #define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */ |
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260 #define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */ |
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261 #define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ |
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262 #define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */ |
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263 #define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */ |
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264 #define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */ |
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265 #define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */ |
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266 #define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */ |
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267 #define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */ |
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268 #define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */ |
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269 #define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */ |
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270 #define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */ |
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271 #define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */ |
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272 #define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */ |
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273 #define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ |
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274 #define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */ |
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275 #define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */ |
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276 #define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ |
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277 #define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */ |
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278 #define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */ |
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279 #define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */ |
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280 #define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ |
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281 #define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */ |
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282 #define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */ |
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283 #define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */ |
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284 #define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */ |
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285 #define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */ |
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286 #define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */ |
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287 #define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */ |
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288 #define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */ |
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289 #define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */ |
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290 #define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */ |
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291 #define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */ |
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292 #define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ |
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293 #define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */ |
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294 #define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */ |
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295 |
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296 /* |
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297 * R22 (0x16) - GPIOCTRL 2 |
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298 */ |
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299 #define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ |
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300 #define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */ |
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301 #define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */ |
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302 #define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */ |
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303 #define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */ |
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304 #define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */ |
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305 #define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */ |
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306 #define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */ |
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307 #define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */ |
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308 #define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */ |
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309 #define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */ |
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310 #define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */ |
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311 #define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */ |
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312 #define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */ |
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313 #define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */ |
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314 #define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */ |
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315 #define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */ |
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316 #define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */ |
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317 #define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */ |
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318 #define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */ |
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319 #define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */ |
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320 #define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */ |
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321 #define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */ |
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322 #define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */ |
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323 #define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */ |
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324 #define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */ |
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325 #define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */ |
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326 #define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */ |
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327 #define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */ |
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328 #define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */ |
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329 #define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */ |
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330 #define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */ |
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331 #define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */ |
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332 #define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */ |
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333 #define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */ |
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334 #define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */ |
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335 #define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */ |
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336 #define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */ |
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337 #define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */ |
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338 #define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */ |
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339 |
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340 /* |
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341 * R23 (0x17) - GPIO_POL |
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342 */ |
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343 #define WM8400_IRQ_INV 0x1000 /* IRQ_INV */ |
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344 #define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */ |
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345 #define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */ |
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346 #define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */ |
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347 #define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */ |
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348 #define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */ |
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349 #define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */ |
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350 #define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */ |
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351 #define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */ |
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352 #define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */ |
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353 #define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */ |
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354 #define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */ |
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355 #define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */ |
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356 #define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */ |
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357 #define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */ |
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358 #define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */ |
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359 #define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */ |
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360 #define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */ |
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361 #define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */ |
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362 #define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */ |
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363 #define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */ |
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364 #define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */ |
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365 #define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */ |
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366 |
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367 /* |
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368 * R65 (0x41) - LDO 1 Control |
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369 */ |
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370 #define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */ |
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371 #define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */ |
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372 #define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */ |
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373 #define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */ |
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374 #define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */ |
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375 #define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */ |
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376 #define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */ |
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377 #define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */ |
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378 #define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */ |
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379 #define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */ |
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380 #define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */ |
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381 #define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */ |
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382 #define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */ |
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383 #define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */ |
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384 #define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */ |
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385 #define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */ |
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386 #define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */ |
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387 #define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */ |
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388 #define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */ |
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389 #define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */ |
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390 #define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */ |
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391 #define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */ |
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392 #define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */ |
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393 #define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */ |
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394 #define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */ |
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395 #define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */ |
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396 |
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397 /* |
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398 * R66 (0x42) - LDO 2 Control |
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399 */ |
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400 #define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */ |
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401 #define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */ |
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402 #define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */ |
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403 #define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ |
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404 #define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */ |
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405 #define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */ |
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406 #define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */ |
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407 #define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */ |
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408 #define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */ |
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409 #define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */ |
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410 #define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */ |
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411 #define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */ |
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412 #define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */ |
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413 #define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */ |
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414 #define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */ |
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415 #define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */ |
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416 #define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */ |
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417 #define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */ |
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418 #define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */ |
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419 #define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */ |
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420 #define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */ |
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421 #define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */ |
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422 #define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */ |
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423 #define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */ |
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424 #define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */ |
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425 #define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */ |
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426 |
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427 /* |
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428 * R67 (0x43) - LDO 3 Control |
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429 */ |
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430 #define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */ |
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431 #define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */ |
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432 #define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */ |
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433 #define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */ |
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434 #define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */ |
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435 #define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */ |
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436 #define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */ |
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437 #define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */ |
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438 #define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */ |
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439 #define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */ |
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440 #define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */ |
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441 #define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */ |
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442 #define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */ |
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443 #define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */ |
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444 #define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */ |
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445 #define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */ |
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446 #define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */ |
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447 #define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */ |
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448 #define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */ |
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449 #define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */ |
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450 #define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */ |
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451 #define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */ |
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452 #define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */ |
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453 #define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */ |
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454 #define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */ |
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455 #define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */ |
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456 |
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457 /* |
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458 * R68 (0x44) - LDO 4 Control |
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459 */ |
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460 #define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */ |
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461 #define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */ |
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462 #define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */ |
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463 #define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */ |
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464 #define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */ |
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465 #define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */ |
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466 #define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */ |
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467 #define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */ |
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468 #define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */ |
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469 #define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */ |
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470 #define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */ |
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471 #define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */ |
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472 #define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */ |
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473 #define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */ |
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474 #define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */ |
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475 #define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */ |
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476 #define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */ |
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477 #define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */ |
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478 #define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */ |
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479 #define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */ |
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480 #define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */ |
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481 #define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */ |
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482 #define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */ |
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483 #define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */ |
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484 #define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */ |
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485 #define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */ |
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486 |
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487 /* |
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488 * R70 (0x46) - DCDC1 Control 1 |
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489 */ |
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490 #define WM8400_DC1_ENA 0x8000 /* DC1_ENA */ |
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491 #define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */ |
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492 #define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */ |
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493 #define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */ |
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494 #define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */ |
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495 #define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */ |
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496 #define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */ |
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497 #define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */ |
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498 #define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */ |
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499 #define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */ |
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500 #define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */ |
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501 #define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */ |
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502 #define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */ |
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503 #define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */ |
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504 #define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */ |
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505 #define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */ |
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506 #define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */ |
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507 #define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */ |
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508 #define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */ |
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509 #define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */ |
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510 #define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */ |
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511 #define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */ |
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512 #define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */ |
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513 #define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */ |
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514 #define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */ |
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515 #define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */ |
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516 #define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */ |
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517 #define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */ |
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518 #define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */ |
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519 #define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */ |
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520 #define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */ |
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521 #define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */ |
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522 #define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */ |
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523 #define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */ |
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524 |
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525 /* |
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526 * R71 (0x47) - DCDC1 Control 2 |
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527 */ |
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528 #define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */ |
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529 #define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */ |
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530 #define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */ |
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531 #define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */ |
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532 #define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */ |
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533 #define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */ |
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534 #define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */ |
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535 #define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */ |
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536 #define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */ |
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537 #define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */ |
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538 #define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */ |
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539 #define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */ |
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540 #define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */ |
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541 #define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */ |
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542 |
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543 /* |
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544 * R72 (0x48) - DCDC2 Control 1 |
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545 */ |
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546 #define WM8400_DC2_ENA 0x8000 /* DC2_ENA */ |
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547 #define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */ |
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548 #define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */ |
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549 #define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */ |
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550 #define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */ |
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551 #define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */ |
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552 #define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */ |
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553 #define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */ |
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554 #define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */ |
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555 #define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */ |
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556 #define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */ |
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557 #define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */ |
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558 #define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */ |
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559 #define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */ |
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560 #define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */ |
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561 #define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */ |
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562 #define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */ |
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563 #define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */ |
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564 #define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */ |
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565 #define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */ |
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566 #define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */ |
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567 #define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */ |
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568 #define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */ |
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569 #define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */ |
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570 #define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */ |
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571 #define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */ |
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572 #define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */ |
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573 #define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */ |
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574 #define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */ |
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575 #define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */ |
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576 #define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */ |
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577 #define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */ |
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578 #define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */ |
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579 #define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */ |
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580 |
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581 /* |
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582 * R73 (0x49) - DCDC2 Control 2 |
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583 */ |
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584 #define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */ |
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585 #define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */ |
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586 #define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */ |
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587 #define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */ |
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588 #define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */ |
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589 #define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */ |
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590 #define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */ |
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591 #define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */ |
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592 #define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */ |
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593 #define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */ |
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594 #define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */ |
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595 #define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */ |
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596 #define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */ |
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597 #define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */ |
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598 |
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599 /* |
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600 * R75 (0x4B) - Interface |
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601 */ |
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602 #define WM8400_AUTOINC 0x0008 /* AUTOINC */ |
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603 #define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */ |
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604 #define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */ |
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605 #define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */ |
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606 #define WM8400_ARA_ENA 0x0004 /* ARA_ENA */ |
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607 #define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */ |
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608 #define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */ |
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609 #define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */ |
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610 #define WM8400_SPI_CFG 0x0002 /* SPI_CFG */ |
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611 #define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */ |
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612 #define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */ |
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613 #define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */ |
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614 |
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615 /* |
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616 * R76 (0x4C) - PM GENERAL |
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617 */ |
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618 #define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */ |
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619 #define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */ |
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620 #define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */ |
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621 #define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */ |
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622 #define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */ |
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623 #define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */ |
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624 #define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */ |
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625 #define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */ |
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626 #define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */ |
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627 #define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */ |
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628 #define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */ |
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629 #define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */ |
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630 #define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */ |
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631 #define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */ |
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632 #define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */ |
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633 #define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */ |
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634 #define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */ |
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635 #define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */ |
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636 #define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */ |
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637 #define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */ |
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638 #define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */ |
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639 #define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */ |
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640 #define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */ |
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641 |
|
642 /* |
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643 * R78 (0x4E) - PM Shutdown Control |
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644 */ |
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645 #define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */ |
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646 #define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */ |
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647 #define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */ |
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648 #define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */ |
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649 #define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */ |
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650 #define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */ |
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651 #define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */ |
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652 #define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */ |
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653 #define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */ |
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654 #define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */ |
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655 #define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */ |
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656 #define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */ |
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657 #define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */ |
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658 #define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */ |
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659 #define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */ |
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660 #define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */ |
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661 |
|
662 /* |
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663 * R79 (0x4F) - Interrupt Status 1 |
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664 */ |
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665 #define WM8400_MICD_CINT 0x8000 /* MICD_CINT */ |
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666 #define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */ |
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667 #define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */ |
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668 #define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */ |
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669 #define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */ |
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670 #define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */ |
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671 #define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */ |
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672 #define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */ |
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673 #define WM8400_JDL_CINT 0x2000 /* JDL_CINT */ |
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674 #define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */ |
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675 #define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */ |
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676 #define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */ |
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677 #define WM8400_JDR_CINT 0x1000 /* JDR_CINT */ |
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678 #define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */ |
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679 #define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */ |
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680 #define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */ |
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681 #define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */ |
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682 #define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */ |
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683 #define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */ |
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684 #define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */ |
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685 #define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */ |
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686 #define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */ |
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687 #define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */ |
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688 #define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */ |
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689 #define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */ |
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690 #define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */ |
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691 #define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */ |
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692 #define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */ |
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693 #define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */ |
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694 #define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */ |
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695 #define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */ |
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696 #define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */ |
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697 #define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */ |
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698 #define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */ |
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699 #define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */ |
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700 #define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */ |
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701 #define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */ |
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702 #define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */ |
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703 #define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */ |
|
704 #define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */ |
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705 #define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */ |
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706 #define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */ |
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707 #define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */ |
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708 #define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */ |
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709 #define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */ |
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710 #define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */ |
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711 #define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */ |
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712 #define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */ |
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713 #define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */ |
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714 #define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */ |
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715 #define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */ |
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716 #define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */ |
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717 #define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */ |
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718 #define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */ |
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719 #define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */ |
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720 #define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */ |
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721 #define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */ |
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722 #define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */ |
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723 #define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */ |
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724 #define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */ |
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725 #define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */ |
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726 #define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */ |
|
727 #define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */ |
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728 #define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */ |
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729 |
|
730 /* |
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731 * R80 (0x50) - Interrupt Status 1 Mask |
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732 */ |
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733 #define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */ |
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734 #define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */ |
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735 #define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */ |
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736 #define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */ |
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737 #define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */ |
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738 #define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */ |
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739 #define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */ |
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740 #define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */ |
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741 #define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */ |
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742 #define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */ |
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743 #define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */ |
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744 #define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */ |
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745 #define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */ |
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746 #define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */ |
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747 #define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */ |
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748 #define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */ |
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749 #define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */ |
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750 #define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */ |
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751 #define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */ |
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752 #define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */ |
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753 #define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */ |
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754 #define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */ |
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755 #define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */ |
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756 #define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */ |
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757 #define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */ |
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758 #define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */ |
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759 #define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */ |
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760 #define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */ |
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761 #define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */ |
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762 #define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */ |
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763 #define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */ |
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764 #define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */ |
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765 #define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */ |
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766 #define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */ |
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767 #define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */ |
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768 #define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */ |
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769 #define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */ |
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770 #define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */ |
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771 #define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */ |
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772 #define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */ |
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773 #define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */ |
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774 #define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */ |
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775 #define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */ |
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776 #define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */ |
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777 #define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */ |
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778 #define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */ |
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779 #define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */ |
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780 #define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */ |
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781 #define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */ |
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782 #define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */ |
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783 #define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */ |
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784 #define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */ |
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785 #define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */ |
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786 #define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */ |
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787 #define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */ |
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788 #define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */ |
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789 #define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */ |
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790 #define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */ |
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791 #define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */ |
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792 #define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */ |
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793 #define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */ |
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794 #define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */ |
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795 #define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */ |
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796 #define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */ |
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797 |
|
798 /* |
|
799 * R81 (0x51) - Interrupt Levels |
|
800 */ |
|
801 #define WM8400_MICD_LVL 0x8000 /* MICD_LVL */ |
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802 #define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */ |
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803 #define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */ |
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804 #define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */ |
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805 #define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */ |
|
806 #define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */ |
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807 #define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */ |
|
808 #define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */ |
|
809 #define WM8400_JDL_LVL 0x2000 /* JDL_LVL */ |
|
810 #define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */ |
|
811 #define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */ |
|
812 #define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */ |
|
813 #define WM8400_JDR_LVL 0x1000 /* JDR_LVL */ |
|
814 #define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */ |
|
815 #define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */ |
|
816 #define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */ |
|
817 #define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */ |
|
818 #define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */ |
|
819 #define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */ |
|
820 #define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */ |
|
821 #define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */ |
|
822 #define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */ |
|
823 #define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */ |
|
824 #define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */ |
|
825 #define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */ |
|
826 #define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */ |
|
827 #define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */ |
|
828 #define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */ |
|
829 #define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */ |
|
830 #define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */ |
|
831 #define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */ |
|
832 #define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */ |
|
833 #define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */ |
|
834 #define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */ |
|
835 #define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */ |
|
836 #define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */ |
|
837 #define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */ |
|
838 #define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */ |
|
839 #define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */ |
|
840 #define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */ |
|
841 #define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */ |
|
842 #define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */ |
|
843 #define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */ |
|
844 #define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */ |
|
845 #define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */ |
|
846 #define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */ |
|
847 #define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */ |
|
848 #define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */ |
|
849 #define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */ |
|
850 #define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */ |
|
851 #define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */ |
|
852 #define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */ |
|
853 #define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */ |
|
854 #define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */ |
|
855 #define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */ |
|
856 #define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */ |
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857 #define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */ |
|
858 #define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */ |
|
859 #define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */ |
|
860 #define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */ |
|
861 #define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */ |
|
862 #define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */ |
|
863 #define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */ |
|
864 #define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */ |
|
865 |
|
866 /* |
|
867 * R82 (0x52) - Shutdown Reason |
|
868 */ |
|
869 #define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */ |
|
870 #define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */ |
|
871 #define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */ |
|
872 #define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */ |
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873 #define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */ |
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874 #define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */ |
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875 #define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */ |
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876 #define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */ |
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877 #define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */ |
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878 #define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */ |
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879 #define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */ |
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880 #define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */ |
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881 #define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */ |
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882 #define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */ |
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883 #define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */ |
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884 #define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */ |
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885 #define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */ |
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886 #define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */ |
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887 #define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */ |
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888 #define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */ |
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889 #define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */ |
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890 #define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */ |
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891 #define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */ |
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892 #define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */ |
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893 #define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */ |
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894 #define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */ |
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895 #define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */ |
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896 #define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */ |
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897 #define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */ |
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898 #define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */ |
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899 #define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */ |
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900 #define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */ |
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901 #define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */ |
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902 #define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */ |
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903 #define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */ |
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904 #define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */ |
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905 #define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */ |
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906 #define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */ |
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907 #define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */ |
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908 #define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */ |
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909 #define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */ |
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910 #define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */ |
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911 #define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */ |
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912 #define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */ |
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913 #define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */ |
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914 #define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */ |
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915 #define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */ |
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916 #define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */ |
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917 |
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918 /* |
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919 * R84 (0x54) - Line Circuits |
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920 */ |
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921 #define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */ |
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922 #define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */ |
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923 #define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */ |
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924 #define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */ |
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925 #define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */ |
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926 #define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */ |
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927 #define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */ |
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928 #define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */ |
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929 #define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */ |
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930 #define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */ |
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931 |
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932 u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg); |
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933 int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data); |
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934 int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val); |
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935 |
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936 #endif |