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1 /* |
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2 * include/linux/mfd/asic3.h |
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3 * |
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4 * Compaq ASIC3 headers. |
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5 * |
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6 * This program is free software; you can redistribute it and/or modify |
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7 * it under the terms of the GNU General Public License version 2 as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * Copyright 2001 Compaq Computer Corporation. |
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11 * Copyright 2007-2008 OpenedHand Ltd. |
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12 */ |
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13 |
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14 #ifndef __ASIC3_H__ |
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15 #define __ASIC3_H__ |
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16 |
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17 #include <linux/types.h> |
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18 |
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19 struct asic3_platform_data { |
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20 u16 *gpio_config; |
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21 unsigned int gpio_config_num; |
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22 |
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23 unsigned int irq_base; |
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24 |
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25 unsigned int gpio_base; |
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26 }; |
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27 |
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28 #define ASIC3_NUM_GPIO_BANKS 4 |
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29 #define ASIC3_GPIOS_PER_BANK 16 |
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30 #define ASIC3_NUM_GPIOS 64 |
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31 #define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6 |
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32 |
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33 #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio)) |
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34 |
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35 #define ASIC3_GPIO_BANK_A 0 |
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36 #define ASIC3_GPIO_BANK_B 1 |
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37 #define ASIC3_GPIO_BANK_C 2 |
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38 #define ASIC3_GPIO_BANK_D 3 |
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39 |
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40 #define ASIC3_GPIO(bank, gpio) \ |
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41 ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio)) |
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42 #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf)) |
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43 /* All offsets below are specified with this address bus shift */ |
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44 #define ASIC3_DEFAULT_ADDR_SHIFT 2 |
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45 |
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46 #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg) |
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47 #define ASIC3_GPIO_OFFSET(base, reg) \ |
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48 (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg) |
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49 |
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50 #define ASIC3_GPIO_A_BASE 0x0000 |
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51 #define ASIC3_GPIO_B_BASE 0x0100 |
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52 #define ASIC3_GPIO_C_BASE 0x0200 |
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53 #define ASIC3_GPIO_D_BASE 0x0300 |
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54 |
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55 #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4) |
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56 #define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \ |
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57 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4))) |
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58 #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio)) |
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59 #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100)) |
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60 #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100)) |
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61 |
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62 #define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */ |
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63 #define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */ |
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64 #define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */ |
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65 #define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */ |
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66 #define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */ |
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67 #define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */ |
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68 #define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */ |
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69 #define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */ |
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70 #define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */ |
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71 #define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */ |
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72 #define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */ |
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73 #define ASIC3_GPIO_SLEEP_CONF 0x2c /* |
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74 * R/W bit 1: autosleep |
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75 * 0: disable gposlpout in normal mode, |
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76 * enable gposlpout in sleep mode. |
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77 */ |
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78 #define ASIC3_GPIO_STATUS 0x30 /* R Pin status */ |
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79 |
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80 /* |
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81 * ASIC3 GPIO config |
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82 * |
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83 * Bits 0..6 gpio number |
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84 * Bits 7..13 Alternate function |
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85 * Bit 14 Direction |
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86 * Bit 15 Initial value |
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87 * |
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88 */ |
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89 #define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f) |
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90 #define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7) |
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91 #define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14) |
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92 #define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15) |
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93 #define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \ |
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94 | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \ |
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95 | (((init) & 0x1) << 15)) |
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96 #define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \ |
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97 ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init)) |
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98 #define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \ |
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99 ASIC3_CONFIG_GPIO((gpio), 0, 1, (init)) |
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100 |
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101 /* |
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102 * Alternate functions |
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103 */ |
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104 #define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0) |
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105 #define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0) |
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106 #define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0) |
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107 #define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0) |
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108 #define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0) |
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109 #define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0) |
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110 #define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0) |
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111 #define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0) |
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112 #define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0) |
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113 #define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0) |
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114 #define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0) |
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115 #define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0) |
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116 #define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0) |
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117 #define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0) |
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118 #define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0) |
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119 #define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0) |
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120 #define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0) |
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121 #define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0) |
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122 #define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0) |
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123 #define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0) |
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124 #define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0) |
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125 #define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0) |
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126 #define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0) |
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127 #define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0) |
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128 |
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129 |
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130 #define ASIC3_SPI_Base 0x0400 |
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131 #define ASIC3_SPI_Control 0x0000 |
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132 #define ASIC3_SPI_TxData 0x0004 |
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133 #define ASIC3_SPI_RxData 0x0008 |
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134 #define ASIC3_SPI_Int 0x000c |
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135 #define ASIC3_SPI_Status 0x0010 |
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136 |
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137 #define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */ |
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138 |
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139 #define ASIC3_PWM_0_Base 0x0500 |
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140 #define ASIC3_PWM_1_Base 0x0600 |
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141 #define ASIC3_PWM_TimeBase 0x0000 |
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142 #define ASIC3_PWM_PeriodTime 0x0004 |
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143 #define ASIC3_PWM_DutyTime 0x0008 |
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144 |
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145 #define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */ |
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146 #define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */ |
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147 |
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148 #define ASIC3_LED_0_Base 0x0700 |
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149 #define ASIC3_LED_1_Base 0x0800 |
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150 #define ASIC3_LED_2_Base 0x0900 |
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151 #define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */ |
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152 #define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */ |
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153 #define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */ |
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154 #define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */ |
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155 |
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156 /* LED TimeBase bits - match ASIC2 */ |
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157 #define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */ |
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158 /* Note: max = 5 on hx4700 */ |
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159 /* 0: maximum time base */ |
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160 /* 1: maximum time base / 2 */ |
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161 /* n: maximum time base / 2^n */ |
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162 |
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163 #define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */ |
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164 #define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ |
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165 #define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ |
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166 |
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167 #define ASIC3_CLOCK_BASE 0x0A00 |
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168 #define ASIC3_CLOCK_CDEX 0x00 |
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169 #define ASIC3_CLOCK_SEL 0x04 |
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170 |
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171 #define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */ |
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172 #define CLOCK_CDEX_SOURCE0 (1 << 0) |
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173 #define CLOCK_CDEX_SOURCE1 (1 << 1) |
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174 #define CLOCK_CDEX_SPI (1 << 2) |
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175 #define CLOCK_CDEX_OWM (1 << 3) |
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176 #define CLOCK_CDEX_PWM0 (1 << 4) |
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177 #define CLOCK_CDEX_PWM1 (1 << 5) |
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178 #define CLOCK_CDEX_LED0 (1 << 6) |
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179 #define CLOCK_CDEX_LED1 (1 << 7) |
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180 #define CLOCK_CDEX_LED2 (1 << 8) |
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181 |
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182 /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */ |
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183 #define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */ |
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184 #define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */ |
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185 #define CLOCK_CDEX_SMBUS (1 << 11) |
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186 #define CLOCK_CDEX_CONTROL_CX (1 << 12) |
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187 |
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188 #define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */ |
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189 #define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */ |
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190 |
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191 #define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */ |
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192 #define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */ |
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193 |
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194 /* R/W: INT clock source control (32.768 kHz) */ |
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195 #define CLOCK_SEL_CX (1 << 2) |
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196 |
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197 |
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198 #define ASIC3_INTR_BASE 0x0B00 |
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199 |
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200 #define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */ |
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201 #define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */ |
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202 #define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */ |
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203 #define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */ |
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204 |
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205 #define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ |
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206 #define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ |
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207 #define ASIC3_INTMASK_MASK0 (1 << 2) |
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208 #define ASIC3_INTMASK_MASK1 (1 << 3) |
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209 #define ASIC3_INTMASK_MASK2 (1 << 4) |
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210 #define ASIC3_INTMASK_MASK3 (1 << 5) |
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211 #define ASIC3_INTMASK_MASK4 (1 << 6) |
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212 #define ASIC3_INTMASK_MASK5 (1 << 7) |
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213 |
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214 #define ASIC3_INTR_PERIPHERAL_A (1 << 0) |
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215 #define ASIC3_INTR_PERIPHERAL_B (1 << 1) |
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216 #define ASIC3_INTR_PERIPHERAL_C (1 << 2) |
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217 #define ASIC3_INTR_PERIPHERAL_D (1 << 3) |
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218 #define ASIC3_INTR_LED0 (1 << 4) |
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219 #define ASIC3_INTR_LED1 (1 << 5) |
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220 #define ASIC3_INTR_LED2 (1 << 6) |
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221 #define ASIC3_INTR_SPI (1 << 7) |
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222 #define ASIC3_INTR_SMBUS (1 << 8) |
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223 #define ASIC3_INTR_OWM (1 << 9) |
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224 |
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225 #define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */ |
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226 #define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */ |
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227 |
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228 |
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229 /* Basic control of the SD ASIC */ |
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230 #define ASIC3_SDHWCTRL_Base 0x0E00 |
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231 #define ASIC3_SDHWCTRL_SDConf 0x00 |
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232 |
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233 #define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */ |
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234 #define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */ |
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235 #define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */ |
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236 #define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */ |
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237 |
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238 /* SD card write protection: 0=high */ |
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239 #define ASIC3_SDHWCTRL_LEVWP (1 << 4) |
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240 #define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */ |
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241 |
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242 /* SD card power supply ctrl 1=enable */ |
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243 #define ASIC3_SDHWCTRL_SDPWR (1 << 6) |
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244 |
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245 #define ASIC3_EXTCF_Base 0x1100 |
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246 |
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247 #define ASIC3_EXTCF_Select 0x00 |
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248 #define ASIC3_EXTCF_Reset 0x04 |
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249 |
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250 #define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */ |
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251 #define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */ |
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252 #define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */ |
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253 #define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */ |
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254 #define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */ |
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255 #define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */ |
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256 #define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */ |
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257 #define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */ |
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258 #define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */ |
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259 #define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */ |
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260 #define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */ |
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261 #define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */ |
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262 #define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14) |
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263 #define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ |
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264 |
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265 /********************************************* |
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266 * The Onewire interface (DS1WM) is handled |
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267 * by the ds1wm driver. |
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268 * |
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269 *********************************************/ |
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270 |
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271 #define ASIC3_OWM_BASE 0xC00 |
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272 |
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273 /***************************************************************************** |
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274 * The SD configuration registers are at a completely different location |
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275 * in memory. They are divided into three sets of registers: |
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276 * |
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277 * SD_CONFIG Core configuration register |
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278 * SD_CTRL Control registers for SD operations |
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279 * SDIO_CTRL Control registers for SDIO operations |
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280 * |
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281 *****************************************************************************/ |
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282 #define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */ |
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283 |
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284 #define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */ |
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285 |
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286 /* [0:8] SD Control Register Base Address */ |
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287 #define ASIC3_SD_CONFIG_Addr0 0x20 |
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288 |
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289 /* [9:31] SD Control Register Base Address */ |
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290 #define ASIC3_SD_CONFIG_Addr1 0x24 |
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291 |
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292 /* R/O: interrupt assigned to pin */ |
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293 #define ASIC3_SD_CONFIG_IntPin 0x78 |
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294 |
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295 /* |
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296 * Set to 0x1f to clock SD controller, 0 otherwise. |
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297 * At 0x82 - Gated Clock Ctrl |
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298 */ |
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299 #define ASIC3_SD_CONFIG_ClkStop 0x80 |
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300 |
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301 /* Control clock of SD controller */ |
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302 #define ASIC3_SD_CONFIG_ClockMode 0x84 |
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303 #define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */ |
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304 #define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */ |
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305 |
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306 /* auto power up after card inserted */ |
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307 #define ASIC3_SD_CONFIG_SDHC_Power2 0x92 |
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308 |
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309 /* auto power down when card removed */ |
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310 #define ASIC3_SD_CONFIG_SDHC_Power3 0x94 |
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311 #define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98 |
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312 #define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */ |
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313 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */ |
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314 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/ |
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315 |
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316 /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */ |
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317 #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8 |
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318 #define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */ |
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319 |
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320 /* Bit 1: double buffer/single buffer */ |
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321 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0 |
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322 |
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323 /* Memory access enable (set to 1 to access SD Controller) */ |
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324 #define SD_CONFIG_COMMAND_MAE (1<<1) |
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325 |
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326 #define SD_CONFIG_CLK_ENABLE_ALL 0x1f |
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327 |
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328 #define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */ |
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329 #define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */ |
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330 |
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331 /* two bits - number of cycles for card detection */ |
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332 #define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3) |
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333 |
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334 |
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335 #define ASIC3_SD_CTRL_Base 0x1000 |
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336 |
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337 #define ASIC3_SD_CTRL_Cmd 0x00 |
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338 #define ASIC3_SD_CTRL_Arg0 0x08 |
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339 #define ASIC3_SD_CTRL_Arg1 0x0C |
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340 #define ASIC3_SD_CTRL_StopInternal 0x10 |
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341 #define ASIC3_SD_CTRL_TransferSectorCount 0x14 |
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342 #define ASIC3_SD_CTRL_Response0 0x18 |
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343 #define ASIC3_SD_CTRL_Response1 0x1C |
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344 #define ASIC3_SD_CTRL_Response2 0x20 |
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345 #define ASIC3_SD_CTRL_Response3 0x24 |
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346 #define ASIC3_SD_CTRL_Response4 0x28 |
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347 #define ASIC3_SD_CTRL_Response5 0x2C |
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348 #define ASIC3_SD_CTRL_Response6 0x30 |
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349 #define ASIC3_SD_CTRL_Response7 0x34 |
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350 #define ASIC3_SD_CTRL_CardStatus 0x38 |
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351 #define ASIC3_SD_CTRL_BufferCtrl 0x3C |
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352 #define ASIC3_SD_CTRL_IntMaskCard 0x40 |
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353 #define ASIC3_SD_CTRL_IntMaskBuffer 0x44 |
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354 #define ASIC3_SD_CTRL_CardClockCtrl 0x48 |
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355 #define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C |
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356 #define ASIC3_SD_CTRL_MemCardOptionSetup 0x50 |
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357 #define ASIC3_SD_CTRL_ErrorStatus0 0x58 |
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358 #define ASIC3_SD_CTRL_ErrorStatus1 0x5C |
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359 #define ASIC3_SD_CTRL_DataPort 0x60 |
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360 #define ASIC3_SD_CTRL_TransactionCtrl 0x68 |
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361 #define ASIC3_SD_CTRL_SoftwareReset 0x1C0 |
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362 |
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363 #define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0) |
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364 |
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365 #define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8) |
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366 |
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367 #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15) |
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368 #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8) |
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369 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7) |
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370 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6) |
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371 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5) |
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372 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4) |
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373 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3) |
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374 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2) |
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375 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1) |
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376 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0) |
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377 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0) |
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378 |
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379 #define MEM_CARD_OPTION_REQUIRED 0x000e |
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380 #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4) |
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381 #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14) |
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382 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15) |
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383 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0 |
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384 |
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385 #define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f) |
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386 #define SD_CTRL_COMMAND_TYPE_CMD (0 << 6) |
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387 #define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6) |
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388 #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6) |
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389 #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8) |
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390 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8) |
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391 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8) |
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392 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8) |
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393 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8) |
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394 #define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11) |
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395 #define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12) |
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396 #define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12) |
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397 #define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13) |
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398 #define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14) |
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399 |
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400 #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0) |
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401 #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8) |
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402 |
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403 #define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0) |
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404 #define SD_CTRL_CARDSTATUS_RW_END (1 << 2) |
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405 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3) |
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406 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4) |
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407 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5) |
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408 #define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7) |
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409 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8) |
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410 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9) |
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411 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10) |
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412 |
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413 #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0) |
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414 #define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1) |
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415 #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2) |
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416 #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3) |
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417 #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4) |
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418 #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5) |
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419 #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6) |
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420 #define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7) |
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421 #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8) |
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422 #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9) |
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423 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13) |
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424 #define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14) |
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425 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15) |
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426 |
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427 #define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0) |
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428 #define SD_CTRL_INTMASKCARD_RW_END (1 << 2) |
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429 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3) |
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430 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4) |
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431 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5) |
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432 #define SD_CTRL_INTMASKCARD_UNK6 (1 << 6) |
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433 #define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7) |
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434 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8) |
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435 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9) |
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436 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10) |
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437 |
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438 #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0) |
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439 #define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1) |
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440 #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2) |
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441 #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3) |
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442 #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4) |
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443 #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5) |
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444 #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6) |
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445 #define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7) |
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446 #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8) |
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447 #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9) |
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448 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13) |
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449 #define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14) |
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450 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15) |
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451 |
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452 #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0) |
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453 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2) |
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454 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3) |
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455 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4) |
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456 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5) |
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457 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8) |
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458 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9) |
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459 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10) |
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460 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11) |
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461 |
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462 #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0) |
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463 #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4) |
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464 #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5) |
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465 #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6) |
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466 |
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467 #define ASIC3_SDIO_CTRL_Base 0x1200 |
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468 |
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469 #define ASIC3_SDIO_CTRL_Cmd 0x00 |
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470 #define ASIC3_SDIO_CTRL_CardPortSel 0x04 |
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471 #define ASIC3_SDIO_CTRL_Arg0 0x08 |
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472 #define ASIC3_SDIO_CTRL_Arg1 0x0C |
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473 #define ASIC3_SDIO_CTRL_TransferBlockCount 0x14 |
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474 #define ASIC3_SDIO_CTRL_Response0 0x18 |
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475 #define ASIC3_SDIO_CTRL_Response1 0x1C |
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476 #define ASIC3_SDIO_CTRL_Response2 0x20 |
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477 #define ASIC3_SDIO_CTRL_Response3 0x24 |
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478 #define ASIC3_SDIO_CTRL_Response4 0x28 |
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479 #define ASIC3_SDIO_CTRL_Response5 0x2C |
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480 #define ASIC3_SDIO_CTRL_Response6 0x30 |
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481 #define ASIC3_SDIO_CTRL_Response7 0x34 |
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482 #define ASIC3_SDIO_CTRL_CardStatus 0x38 |
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483 #define ASIC3_SDIO_CTRL_BufferCtrl 0x3C |
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484 #define ASIC3_SDIO_CTRL_IntMaskCard 0x40 |
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485 #define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44 |
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486 #define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C |
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487 #define ASIC3_SDIO_CTRL_CardOptionSetup 0x50 |
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488 #define ASIC3_SDIO_CTRL_ErrorStatus0 0x54 |
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489 #define ASIC3_SDIO_CTRL_ErrorStatus1 0x58 |
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490 #define ASIC3_SDIO_CTRL_DataPort 0x60 |
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491 #define ASIC3_SDIO_CTRL_TransactionCtrl 0x68 |
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492 #define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C |
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493 #define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70 |
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494 #define ASIC3_SDIO_CTRL_HostInformation 0x74 |
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495 #define ASIC3_SDIO_CTRL_ErrorCtrl 0x78 |
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496 #define ASIC3_SDIO_CTRL_LEDCtrl 0x7C |
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497 #define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0 |
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498 |
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499 #define ASIC3_MAP_SIZE_32BIT 0x2000 |
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500 #define ASIC3_MAP_SIZE_16BIT 0x1000 |
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501 |
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502 #endif /* __ASIC3_H__ */ |