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1 #ifndef __LINUX_ATMEL_PWM_H |
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2 #define __LINUX_ATMEL_PWM_H |
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3 |
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4 /** |
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5 * struct pwm_channel - driver handle to a PWM channel |
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6 * @regs: base of this channel's registers |
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7 * @index: number of this channel (0..31) |
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8 * @mck: base clock rate, which can be prescaled and maybe subdivided |
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9 * |
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10 * Drivers initialize a pwm_channel structure using pwm_channel_alloc(). |
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11 * Then they configure its clock rate (derived from MCK), alignment, |
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12 * polarity, and duty cycle by writing directly to the channel registers, |
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13 * before enabling the channel by calling pwm_channel_enable(). |
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14 * |
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15 * After emitting a PWM signal for the desired length of time, drivers |
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16 * may then pwm_channel_disable() or pwm_channel_free(). Both of these |
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17 * disable the channel, but when it's freed the IRQ is deconfigured and |
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18 * the channel must later be re-allocated and reconfigured. |
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19 * |
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20 * Note that if the period or duty cycle need to be changed while the |
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21 * PWM channel is operating, drivers must use the PWM_CUPD double buffer |
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22 * mechanism, either polling until they change or getting implicitly |
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23 * notified through a once-per-period interrupt handler. |
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24 */ |
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25 struct pwm_channel { |
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26 void __iomem *regs; |
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27 unsigned index; |
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28 unsigned long mck; |
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29 }; |
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30 |
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31 extern int pwm_channel_alloc(int index, struct pwm_channel *ch); |
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32 extern int pwm_channel_free(struct pwm_channel *ch); |
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33 |
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34 extern int pwm_clk_alloc(unsigned prescale, unsigned div); |
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35 extern void pwm_clk_free(unsigned clk); |
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36 |
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37 extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled); |
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38 |
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39 #define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1) |
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40 #define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0) |
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41 |
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42 /* periodic interrupts, mostly for CUPD changes to period or cycle */ |
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43 extern int pwm_channel_handler(struct pwm_channel *ch, |
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44 void (*handler)(struct pwm_channel *ch)); |
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45 |
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46 /* per-channel registers (banked at pwm_channel->regs) */ |
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47 #define PWM_CMR 0x00 /* mode register */ |
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48 #define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */ |
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49 #define PWM_CPR_CPOL (1 << 9) /* set: idle high */ |
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50 #define PWM_CPR_CALG (1 << 8) /* set: center align */ |
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51 #define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */ |
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52 #define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */ |
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53 #define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */ |
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54 #define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */ |
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55 #define PWM_CPRD 0x08 /* period (count up from zero) */ |
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56 #define PWM_CCNT 0x0c /* counter (20 bits?) */ |
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57 #define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */ |
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58 |
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59 static inline void |
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60 pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val) |
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61 { |
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62 __raw_writel(val, pwmc->regs + offset); |
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63 } |
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64 |
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65 static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset) |
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66 { |
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67 return __raw_readl(pwmc->regs + offset); |
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68 } |
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69 |
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70 #endif /* __LINUX_ATMEL_PWM_H */ |