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1 #ifndef __INCLUDE_ATMEL_SSC_H |
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2 #define __INCLUDE_ATMEL_SSC_H |
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3 |
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4 #include <linux/platform_device.h> |
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5 #include <linux/list.h> |
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6 |
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7 struct ssc_device { |
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8 struct list_head list; |
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9 void __iomem *regs; |
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10 struct platform_device *pdev; |
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11 struct clk *clk; |
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12 int user; |
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13 int irq; |
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14 }; |
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15 |
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16 struct ssc_device * __must_check ssc_request(unsigned int ssc_num); |
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17 void ssc_free(struct ssc_device *ssc); |
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18 |
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19 /* SSC register offsets */ |
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20 |
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21 /* SSC Control Register */ |
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22 #define SSC_CR 0x00000000 |
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23 #define SSC_CR_RXDIS_SIZE 1 |
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24 #define SSC_CR_RXDIS_OFFSET 1 |
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25 #define SSC_CR_RXEN_SIZE 1 |
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26 #define SSC_CR_RXEN_OFFSET 0 |
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27 #define SSC_CR_SWRST_SIZE 1 |
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28 #define SSC_CR_SWRST_OFFSET 15 |
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29 #define SSC_CR_TXDIS_SIZE 1 |
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30 #define SSC_CR_TXDIS_OFFSET 9 |
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31 #define SSC_CR_TXEN_SIZE 1 |
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32 #define SSC_CR_TXEN_OFFSET 8 |
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33 |
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34 /* SSC Clock Mode Register */ |
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35 #define SSC_CMR 0x00000004 |
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36 #define SSC_CMR_DIV_SIZE 12 |
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37 #define SSC_CMR_DIV_OFFSET 0 |
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38 |
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39 /* SSC Receive Clock Mode Register */ |
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40 #define SSC_RCMR 0x00000010 |
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41 #define SSC_RCMR_CKG_SIZE 2 |
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42 #define SSC_RCMR_CKG_OFFSET 6 |
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43 #define SSC_RCMR_CKI_SIZE 1 |
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44 #define SSC_RCMR_CKI_OFFSET 5 |
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45 #define SSC_RCMR_CKO_SIZE 3 |
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46 #define SSC_RCMR_CKO_OFFSET 2 |
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47 #define SSC_RCMR_CKS_SIZE 2 |
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48 #define SSC_RCMR_CKS_OFFSET 0 |
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49 #define SSC_RCMR_PERIOD_SIZE 8 |
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50 #define SSC_RCMR_PERIOD_OFFSET 24 |
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51 #define SSC_RCMR_START_SIZE 4 |
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52 #define SSC_RCMR_START_OFFSET 8 |
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53 #define SSC_RCMR_STOP_SIZE 1 |
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54 #define SSC_RCMR_STOP_OFFSET 12 |
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55 #define SSC_RCMR_STTDLY_SIZE 8 |
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56 #define SSC_RCMR_STTDLY_OFFSET 16 |
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57 |
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58 /* SSC Receive Frame Mode Register */ |
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59 #define SSC_RFMR 0x00000014 |
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60 #define SSC_RFMR_DATLEN_SIZE 5 |
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61 #define SSC_RFMR_DATLEN_OFFSET 0 |
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62 #define SSC_RFMR_DATNB_SIZE 4 |
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63 #define SSC_RFMR_DATNB_OFFSET 8 |
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64 #define SSC_RFMR_FSEDGE_SIZE 1 |
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65 #define SSC_RFMR_FSEDGE_OFFSET 24 |
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66 #define SSC_RFMR_FSLEN_SIZE 4 |
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67 #define SSC_RFMR_FSLEN_OFFSET 16 |
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68 #define SSC_RFMR_FSOS_SIZE 4 |
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69 #define SSC_RFMR_FSOS_OFFSET 20 |
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70 #define SSC_RFMR_LOOP_SIZE 1 |
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71 #define SSC_RFMR_LOOP_OFFSET 5 |
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72 #define SSC_RFMR_MSBF_SIZE 1 |
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73 #define SSC_RFMR_MSBF_OFFSET 7 |
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74 |
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75 /* SSC Transmit Clock Mode Register */ |
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76 #define SSC_TCMR 0x00000018 |
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77 #define SSC_TCMR_CKG_SIZE 2 |
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78 #define SSC_TCMR_CKG_OFFSET 6 |
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79 #define SSC_TCMR_CKI_SIZE 1 |
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80 #define SSC_TCMR_CKI_OFFSET 5 |
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81 #define SSC_TCMR_CKO_SIZE 3 |
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82 #define SSC_TCMR_CKO_OFFSET 2 |
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83 #define SSC_TCMR_CKS_SIZE 2 |
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84 #define SSC_TCMR_CKS_OFFSET 0 |
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85 #define SSC_TCMR_PERIOD_SIZE 8 |
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86 #define SSC_TCMR_PERIOD_OFFSET 24 |
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87 #define SSC_TCMR_START_SIZE 4 |
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88 #define SSC_TCMR_START_OFFSET 8 |
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89 #define SSC_TCMR_STTDLY_SIZE 8 |
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90 #define SSC_TCMR_STTDLY_OFFSET 16 |
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91 |
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92 /* SSC Transmit Frame Mode Register */ |
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93 #define SSC_TFMR 0x0000001c |
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94 #define SSC_TFMR_DATDEF_SIZE 1 |
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95 #define SSC_TFMR_DATDEF_OFFSET 5 |
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96 #define SSC_TFMR_DATLEN_SIZE 5 |
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97 #define SSC_TFMR_DATLEN_OFFSET 0 |
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98 #define SSC_TFMR_DATNB_SIZE 4 |
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99 #define SSC_TFMR_DATNB_OFFSET 8 |
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100 #define SSC_TFMR_FSDEN_SIZE 1 |
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101 #define SSC_TFMR_FSDEN_OFFSET 23 |
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102 #define SSC_TFMR_FSEDGE_SIZE 1 |
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103 #define SSC_TFMR_FSEDGE_OFFSET 24 |
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104 #define SSC_TFMR_FSLEN_SIZE 4 |
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105 #define SSC_TFMR_FSLEN_OFFSET 16 |
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106 #define SSC_TFMR_FSOS_SIZE 3 |
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107 #define SSC_TFMR_FSOS_OFFSET 20 |
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108 #define SSC_TFMR_MSBF_SIZE 1 |
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109 #define SSC_TFMR_MSBF_OFFSET 7 |
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110 |
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111 /* SSC Receive Hold Register */ |
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112 #define SSC_RHR 0x00000020 |
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113 #define SSC_RHR_RDAT_SIZE 32 |
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114 #define SSC_RHR_RDAT_OFFSET 0 |
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115 |
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116 /* SSC Transmit Hold Register */ |
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117 #define SSC_THR 0x00000024 |
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118 #define SSC_THR_TDAT_SIZE 32 |
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119 #define SSC_THR_TDAT_OFFSET 0 |
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120 |
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121 /* SSC Receive Sync. Holding Register */ |
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122 #define SSC_RSHR 0x00000030 |
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123 #define SSC_RSHR_RSDAT_SIZE 16 |
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124 #define SSC_RSHR_RSDAT_OFFSET 0 |
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125 |
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126 /* SSC Transmit Sync. Holding Register */ |
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127 #define SSC_TSHR 0x00000034 |
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128 #define SSC_TSHR_TSDAT_SIZE 16 |
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129 #define SSC_TSHR_RSDAT_OFFSET 0 |
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130 |
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131 /* SSC Receive Compare 0 Register */ |
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132 #define SSC_RC0R 0x00000038 |
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133 #define SSC_RC0R_CP0_SIZE 16 |
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134 #define SSC_RC0R_CP0_OFFSET 0 |
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135 |
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136 /* SSC Receive Compare 1 Register */ |
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137 #define SSC_RC1R 0x0000003c |
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138 #define SSC_RC1R_CP1_SIZE 16 |
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139 #define SSC_RC1R_CP1_OFFSET 0 |
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140 |
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141 /* SSC Status Register */ |
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142 #define SSC_SR 0x00000040 |
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143 #define SSC_SR_CP0_SIZE 1 |
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144 #define SSC_SR_CP0_OFFSET 8 |
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145 #define SSC_SR_CP1_SIZE 1 |
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146 #define SSC_SR_CP1_OFFSET 9 |
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147 #define SSC_SR_ENDRX_SIZE 1 |
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148 #define SSC_SR_ENDRX_OFFSET 6 |
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149 #define SSC_SR_ENDTX_SIZE 1 |
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150 #define SSC_SR_ENDTX_OFFSET 2 |
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151 #define SSC_SR_OVRUN_SIZE 1 |
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152 #define SSC_SR_OVRUN_OFFSET 5 |
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153 #define SSC_SR_RXBUFF_SIZE 1 |
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154 #define SSC_SR_RXBUFF_OFFSET 7 |
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155 #define SSC_SR_RXEN_SIZE 1 |
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156 #define SSC_SR_RXEN_OFFSET 17 |
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157 #define SSC_SR_RXRDY_SIZE 1 |
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158 #define SSC_SR_RXRDY_OFFSET 4 |
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159 #define SSC_SR_RXSYN_SIZE 1 |
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160 #define SSC_SR_RXSYN_OFFSET 11 |
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161 #define SSC_SR_TXBUFE_SIZE 1 |
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162 #define SSC_SR_TXBUFE_OFFSET 3 |
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163 #define SSC_SR_TXEMPTY_SIZE 1 |
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164 #define SSC_SR_TXEMPTY_OFFSET 1 |
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165 #define SSC_SR_TXEN_SIZE 1 |
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166 #define SSC_SR_TXEN_OFFSET 16 |
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167 #define SSC_SR_TXRDY_SIZE 1 |
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168 #define SSC_SR_TXRDY_OFFSET 0 |
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169 #define SSC_SR_TXSYN_SIZE 1 |
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170 #define SSC_SR_TXSYN_OFFSET 10 |
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171 |
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172 /* SSC Interrupt Enable Register */ |
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173 #define SSC_IER 0x00000044 |
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174 #define SSC_IER_CP0_SIZE 1 |
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175 #define SSC_IER_CP0_OFFSET 8 |
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176 #define SSC_IER_CP1_SIZE 1 |
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177 #define SSC_IER_CP1_OFFSET 9 |
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178 #define SSC_IER_ENDRX_SIZE 1 |
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179 #define SSC_IER_ENDRX_OFFSET 6 |
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180 #define SSC_IER_ENDTX_SIZE 1 |
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181 #define SSC_IER_ENDTX_OFFSET 2 |
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182 #define SSC_IER_OVRUN_SIZE 1 |
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183 #define SSC_IER_OVRUN_OFFSET 5 |
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184 #define SSC_IER_RXBUFF_SIZE 1 |
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185 #define SSC_IER_RXBUFF_OFFSET 7 |
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186 #define SSC_IER_RXRDY_SIZE 1 |
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187 #define SSC_IER_RXRDY_OFFSET 4 |
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188 #define SSC_IER_RXSYN_SIZE 1 |
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189 #define SSC_IER_RXSYN_OFFSET 11 |
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190 #define SSC_IER_TXBUFE_SIZE 1 |
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191 #define SSC_IER_TXBUFE_OFFSET 3 |
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192 #define SSC_IER_TXEMPTY_SIZE 1 |
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193 #define SSC_IER_TXEMPTY_OFFSET 1 |
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194 #define SSC_IER_TXRDY_SIZE 1 |
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195 #define SSC_IER_TXRDY_OFFSET 0 |
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196 #define SSC_IER_TXSYN_SIZE 1 |
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197 #define SSC_IER_TXSYN_OFFSET 10 |
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198 |
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199 /* SSC Interrupt Disable Register */ |
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200 #define SSC_IDR 0x00000048 |
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201 #define SSC_IDR_CP0_SIZE 1 |
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202 #define SSC_IDR_CP0_OFFSET 8 |
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203 #define SSC_IDR_CP1_SIZE 1 |
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204 #define SSC_IDR_CP1_OFFSET 9 |
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205 #define SSC_IDR_ENDRX_SIZE 1 |
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206 #define SSC_IDR_ENDRX_OFFSET 6 |
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207 #define SSC_IDR_ENDTX_SIZE 1 |
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208 #define SSC_IDR_ENDTX_OFFSET 2 |
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209 #define SSC_IDR_OVRUN_SIZE 1 |
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210 #define SSC_IDR_OVRUN_OFFSET 5 |
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211 #define SSC_IDR_RXBUFF_SIZE 1 |
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212 #define SSC_IDR_RXBUFF_OFFSET 7 |
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213 #define SSC_IDR_RXRDY_SIZE 1 |
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214 #define SSC_IDR_RXRDY_OFFSET 4 |
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215 #define SSC_IDR_RXSYN_SIZE 1 |
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216 #define SSC_IDR_RXSYN_OFFSET 11 |
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217 #define SSC_IDR_TXBUFE_SIZE 1 |
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218 #define SSC_IDR_TXBUFE_OFFSET 3 |
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219 #define SSC_IDR_TXEMPTY_SIZE 1 |
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220 #define SSC_IDR_TXEMPTY_OFFSET 1 |
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221 #define SSC_IDR_TXRDY_SIZE 1 |
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222 #define SSC_IDR_TXRDY_OFFSET 0 |
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223 #define SSC_IDR_TXSYN_SIZE 1 |
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224 #define SSC_IDR_TXSYN_OFFSET 10 |
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225 |
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226 /* SSC Interrupt Mask Register */ |
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227 #define SSC_IMR 0x0000004c |
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228 #define SSC_IMR_CP0_SIZE 1 |
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229 #define SSC_IMR_CP0_OFFSET 8 |
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230 #define SSC_IMR_CP1_SIZE 1 |
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231 #define SSC_IMR_CP1_OFFSET 9 |
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232 #define SSC_IMR_ENDRX_SIZE 1 |
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233 #define SSC_IMR_ENDRX_OFFSET 6 |
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234 #define SSC_IMR_ENDTX_SIZE 1 |
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235 #define SSC_IMR_ENDTX_OFFSET 2 |
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236 #define SSC_IMR_OVRUN_SIZE 1 |
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237 #define SSC_IMR_OVRUN_OFFSET 5 |
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238 #define SSC_IMR_RXBUFF_SIZE 1 |
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239 #define SSC_IMR_RXBUFF_OFFSET 7 |
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240 #define SSC_IMR_RXRDY_SIZE 1 |
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241 #define SSC_IMR_RXRDY_OFFSET 4 |
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242 #define SSC_IMR_RXSYN_SIZE 1 |
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243 #define SSC_IMR_RXSYN_OFFSET 11 |
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244 #define SSC_IMR_TXBUFE_SIZE 1 |
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245 #define SSC_IMR_TXBUFE_OFFSET 3 |
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246 #define SSC_IMR_TXEMPTY_SIZE 1 |
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247 #define SSC_IMR_TXEMPTY_OFFSET 1 |
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248 #define SSC_IMR_TXRDY_SIZE 1 |
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249 #define SSC_IMR_TXRDY_OFFSET 0 |
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250 #define SSC_IMR_TXSYN_SIZE 1 |
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251 #define SSC_IMR_TXSYN_OFFSET 10 |
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252 |
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253 /* SSC PDC Receive Pointer Register */ |
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254 #define SSC_PDC_RPR 0x00000100 |
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255 |
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256 /* SSC PDC Receive Counter Register */ |
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257 #define SSC_PDC_RCR 0x00000104 |
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258 |
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259 /* SSC PDC Transmit Pointer Register */ |
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260 #define SSC_PDC_TPR 0x00000108 |
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261 |
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262 /* SSC PDC Receive Next Pointer Register */ |
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263 #define SSC_PDC_RNPR 0x00000110 |
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264 |
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265 /* SSC PDC Receive Next Counter Register */ |
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266 #define SSC_PDC_RNCR 0x00000114 |
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267 |
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268 /* SSC PDC Transmit Counter Register */ |
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269 #define SSC_PDC_TCR 0x0000010c |
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270 |
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271 /* SSC PDC Transmit Next Pointer Register */ |
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272 #define SSC_PDC_TNPR 0x00000118 |
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273 |
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274 /* SSC PDC Transmit Next Counter Register */ |
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275 #define SSC_PDC_TNCR 0x0000011c |
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276 |
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277 /* SSC PDC Transfer Control Register */ |
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278 #define SSC_PDC_PTCR 0x00000120 |
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279 #define SSC_PDC_PTCR_RXTDIS_SIZE 1 |
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280 #define SSC_PDC_PTCR_RXTDIS_OFFSET 1 |
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281 #define SSC_PDC_PTCR_RXTEN_SIZE 1 |
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282 #define SSC_PDC_PTCR_RXTEN_OFFSET 0 |
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283 #define SSC_PDC_PTCR_TXTDIS_SIZE 1 |
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284 #define SSC_PDC_PTCR_TXTDIS_OFFSET 9 |
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285 #define SSC_PDC_PTCR_TXTEN_SIZE 1 |
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286 #define SSC_PDC_PTCR_TXTEN_OFFSET 8 |
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287 |
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288 /* SSC PDC Transfer Status Register */ |
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289 #define SSC_PDC_PTSR 0x00000124 |
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290 #define SSC_PDC_PTSR_RXTEN_SIZE 1 |
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291 #define SSC_PDC_PTSR_RXTEN_OFFSET 0 |
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292 #define SSC_PDC_PTSR_TXTEN_SIZE 1 |
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293 #define SSC_PDC_PTSR_TXTEN_OFFSET 8 |
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294 |
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295 /* Bit manipulation macros */ |
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296 #define SSC_BIT(name) \ |
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297 (1 << SSC_##name##_OFFSET) |
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298 #define SSC_BF(name, value) \ |
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299 (((value) & ((1 << SSC_##name##_SIZE) - 1)) \ |
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300 << SSC_##name##_OFFSET) |
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301 #define SSC_BFEXT(name, value) \ |
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302 (((value) >> SSC_##name##_OFFSET) \ |
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303 & ((1 << SSC_##name##_SIZE) - 1)) |
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304 #define SSC_BFINS(name, value, old) \ |
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305 (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \ |
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306 << SSC_##name##_OFFSET)) | SSC_BF(name, value)) |
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307 |
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308 /* Register access macros */ |
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309 #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) |
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310 #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) |
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311 |
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312 #endif /* __INCLUDE_ATMEL_SSC_H */ |