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1 #ifndef _ASM_X86_XOR_32_H |
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2 #define _ASM_X86_XOR_32_H |
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3 |
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4 /* |
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5 * Optimized RAID-5 checksumming functions for MMX and SSE. |
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6 * |
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7 * This program is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2, or (at your option) |
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10 * any later version. |
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11 * |
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12 * You should have received a copy of the GNU General Public License |
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13 * (for example /usr/src/linux/COPYING); if not, write to the Free |
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14 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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15 */ |
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16 |
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17 /* |
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18 * High-speed RAID5 checksumming functions utilizing MMX instructions. |
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19 * Copyright (C) 1998 Ingo Molnar. |
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20 */ |
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21 |
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22 #define LD(x, y) " movq 8*("#x")(%1), %%mm"#y" ;\n" |
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23 #define ST(x, y) " movq %%mm"#y", 8*("#x")(%1) ;\n" |
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24 #define XO1(x, y) " pxor 8*("#x")(%2), %%mm"#y" ;\n" |
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25 #define XO2(x, y) " pxor 8*("#x")(%3), %%mm"#y" ;\n" |
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26 #define XO3(x, y) " pxor 8*("#x")(%4), %%mm"#y" ;\n" |
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27 #define XO4(x, y) " pxor 8*("#x")(%5), %%mm"#y" ;\n" |
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28 |
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29 #include <asm/i387.h> |
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30 |
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31 static void |
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32 xor_pII_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) |
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33 { |
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34 unsigned long lines = bytes >> 7; |
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35 |
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36 kernel_fpu_begin(); |
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37 |
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38 asm volatile( |
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39 #undef BLOCK |
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40 #define BLOCK(i) \ |
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41 LD(i, 0) \ |
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42 LD(i + 1, 1) \ |
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43 LD(i + 2, 2) \ |
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44 LD(i + 3, 3) \ |
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45 XO1(i, 0) \ |
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46 ST(i, 0) \ |
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47 XO1(i+1, 1) \ |
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48 ST(i+1, 1) \ |
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49 XO1(i + 2, 2) \ |
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50 ST(i + 2, 2) \ |
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51 XO1(i + 3, 3) \ |
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52 ST(i + 3, 3) |
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53 |
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54 " .align 32 ;\n" |
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55 " 1: ;\n" |
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56 |
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57 BLOCK(0) |
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58 BLOCK(4) |
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59 BLOCK(8) |
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60 BLOCK(12) |
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61 |
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62 " addl $128, %1 ;\n" |
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63 " addl $128, %2 ;\n" |
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64 " decl %0 ;\n" |
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65 " jnz 1b ;\n" |
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66 : "+r" (lines), |
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67 "+r" (p1), "+r" (p2) |
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68 : |
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69 : "memory"); |
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70 |
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71 kernel_fpu_end(); |
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72 } |
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73 |
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74 static void |
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75 xor_pII_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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76 unsigned long *p3) |
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77 { |
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78 unsigned long lines = bytes >> 7; |
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79 |
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80 kernel_fpu_begin(); |
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81 |
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82 asm volatile( |
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83 #undef BLOCK |
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84 #define BLOCK(i) \ |
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85 LD(i, 0) \ |
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86 LD(i + 1, 1) \ |
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87 LD(i + 2, 2) \ |
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88 LD(i + 3, 3) \ |
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89 XO1(i, 0) \ |
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90 XO1(i + 1, 1) \ |
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91 XO1(i + 2, 2) \ |
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92 XO1(i + 3, 3) \ |
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93 XO2(i, 0) \ |
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94 ST(i, 0) \ |
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95 XO2(i + 1, 1) \ |
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96 ST(i + 1, 1) \ |
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97 XO2(i + 2, 2) \ |
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98 ST(i + 2, 2) \ |
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99 XO2(i + 3, 3) \ |
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100 ST(i + 3, 3) |
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101 |
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102 " .align 32 ;\n" |
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103 " 1: ;\n" |
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104 |
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105 BLOCK(0) |
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106 BLOCK(4) |
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107 BLOCK(8) |
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108 BLOCK(12) |
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109 |
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110 " addl $128, %1 ;\n" |
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111 " addl $128, %2 ;\n" |
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112 " addl $128, %3 ;\n" |
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113 " decl %0 ;\n" |
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114 " jnz 1b ;\n" |
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115 : "+r" (lines), |
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116 "+r" (p1), "+r" (p2), "+r" (p3) |
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117 : |
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118 : "memory"); |
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119 |
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120 kernel_fpu_end(); |
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121 } |
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122 |
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123 static void |
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124 xor_pII_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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125 unsigned long *p3, unsigned long *p4) |
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126 { |
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127 unsigned long lines = bytes >> 7; |
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128 |
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129 kernel_fpu_begin(); |
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130 |
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131 asm volatile( |
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132 #undef BLOCK |
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133 #define BLOCK(i) \ |
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134 LD(i, 0) \ |
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135 LD(i + 1, 1) \ |
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136 LD(i + 2, 2) \ |
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137 LD(i + 3, 3) \ |
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138 XO1(i, 0) \ |
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139 XO1(i + 1, 1) \ |
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140 XO1(i + 2, 2) \ |
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141 XO1(i + 3, 3) \ |
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142 XO2(i, 0) \ |
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143 XO2(i + 1, 1) \ |
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144 XO2(i + 2, 2) \ |
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145 XO2(i + 3, 3) \ |
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146 XO3(i, 0) \ |
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147 ST(i, 0) \ |
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148 XO3(i + 1, 1) \ |
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149 ST(i + 1, 1) \ |
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150 XO3(i + 2, 2) \ |
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151 ST(i + 2, 2) \ |
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152 XO3(i + 3, 3) \ |
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153 ST(i + 3, 3) |
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154 |
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155 " .align 32 ;\n" |
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156 " 1: ;\n" |
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157 |
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158 BLOCK(0) |
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159 BLOCK(4) |
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160 BLOCK(8) |
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161 BLOCK(12) |
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162 |
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163 " addl $128, %1 ;\n" |
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164 " addl $128, %2 ;\n" |
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165 " addl $128, %3 ;\n" |
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166 " addl $128, %4 ;\n" |
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167 " decl %0 ;\n" |
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168 " jnz 1b ;\n" |
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169 : "+r" (lines), |
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170 "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) |
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171 : |
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172 : "memory"); |
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173 |
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174 kernel_fpu_end(); |
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175 } |
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176 |
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177 |
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178 static void |
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179 xor_pII_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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180 unsigned long *p3, unsigned long *p4, unsigned long *p5) |
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181 { |
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182 unsigned long lines = bytes >> 7; |
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183 |
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184 kernel_fpu_begin(); |
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185 |
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186 /* Make sure GCC forgets anything it knows about p4 or p5, |
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187 such that it won't pass to the asm volatile below a |
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188 register that is shared with any other variable. That's |
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189 because we modify p4 and p5 there, but we can't mark them |
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190 as read/write, otherwise we'd overflow the 10-asm-operands |
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191 limit of GCC < 3.1. */ |
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192 asm("" : "+r" (p4), "+r" (p5)); |
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193 |
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194 asm volatile( |
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195 #undef BLOCK |
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196 #define BLOCK(i) \ |
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197 LD(i, 0) \ |
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198 LD(i + 1, 1) \ |
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199 LD(i + 2, 2) \ |
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200 LD(i + 3, 3) \ |
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201 XO1(i, 0) \ |
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202 XO1(i + 1, 1) \ |
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203 XO1(i + 2, 2) \ |
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204 XO1(i + 3, 3) \ |
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205 XO2(i, 0) \ |
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206 XO2(i + 1, 1) \ |
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207 XO2(i + 2, 2) \ |
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208 XO2(i + 3, 3) \ |
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209 XO3(i, 0) \ |
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210 XO3(i + 1, 1) \ |
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211 XO3(i + 2, 2) \ |
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212 XO3(i + 3, 3) \ |
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213 XO4(i, 0) \ |
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214 ST(i, 0) \ |
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215 XO4(i + 1, 1) \ |
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216 ST(i + 1, 1) \ |
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217 XO4(i + 2, 2) \ |
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218 ST(i + 2, 2) \ |
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219 XO4(i + 3, 3) \ |
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220 ST(i + 3, 3) |
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221 |
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222 " .align 32 ;\n" |
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223 " 1: ;\n" |
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224 |
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225 BLOCK(0) |
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226 BLOCK(4) |
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227 BLOCK(8) |
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228 BLOCK(12) |
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229 |
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230 " addl $128, %1 ;\n" |
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231 " addl $128, %2 ;\n" |
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232 " addl $128, %3 ;\n" |
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233 " addl $128, %4 ;\n" |
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234 " addl $128, %5 ;\n" |
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235 " decl %0 ;\n" |
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236 " jnz 1b ;\n" |
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237 : "+r" (lines), |
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238 "+r" (p1), "+r" (p2), "+r" (p3) |
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239 : "r" (p4), "r" (p5) |
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240 : "memory"); |
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241 |
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242 /* p4 and p5 were modified, and now the variables are dead. |
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243 Clobber them just to be sure nobody does something stupid |
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244 like assuming they have some legal value. */ |
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245 asm("" : "=r" (p4), "=r" (p5)); |
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246 |
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247 kernel_fpu_end(); |
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248 } |
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249 |
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250 #undef LD |
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251 #undef XO1 |
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252 #undef XO2 |
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253 #undef XO3 |
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254 #undef XO4 |
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255 #undef ST |
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256 #undef BLOCK |
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257 |
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258 static void |
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259 xor_p5_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) |
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260 { |
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261 unsigned long lines = bytes >> 6; |
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262 |
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263 kernel_fpu_begin(); |
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264 |
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265 asm volatile( |
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266 " .align 32 ;\n" |
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267 " 1: ;\n" |
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268 " movq (%1), %%mm0 ;\n" |
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269 " movq 8(%1), %%mm1 ;\n" |
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270 " pxor (%2), %%mm0 ;\n" |
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271 " movq 16(%1), %%mm2 ;\n" |
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272 " movq %%mm0, (%1) ;\n" |
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273 " pxor 8(%2), %%mm1 ;\n" |
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274 " movq 24(%1), %%mm3 ;\n" |
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275 " movq %%mm1, 8(%1) ;\n" |
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276 " pxor 16(%2), %%mm2 ;\n" |
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277 " movq 32(%1), %%mm4 ;\n" |
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278 " movq %%mm2, 16(%1) ;\n" |
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279 " pxor 24(%2), %%mm3 ;\n" |
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280 " movq 40(%1), %%mm5 ;\n" |
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281 " movq %%mm3, 24(%1) ;\n" |
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282 " pxor 32(%2), %%mm4 ;\n" |
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283 " movq 48(%1), %%mm6 ;\n" |
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284 " movq %%mm4, 32(%1) ;\n" |
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285 " pxor 40(%2), %%mm5 ;\n" |
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286 " movq 56(%1), %%mm7 ;\n" |
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287 " movq %%mm5, 40(%1) ;\n" |
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288 " pxor 48(%2), %%mm6 ;\n" |
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289 " pxor 56(%2), %%mm7 ;\n" |
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290 " movq %%mm6, 48(%1) ;\n" |
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291 " movq %%mm7, 56(%1) ;\n" |
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292 |
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293 " addl $64, %1 ;\n" |
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294 " addl $64, %2 ;\n" |
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295 " decl %0 ;\n" |
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296 " jnz 1b ;\n" |
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297 : "+r" (lines), |
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298 "+r" (p1), "+r" (p2) |
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299 : |
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300 : "memory"); |
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301 |
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302 kernel_fpu_end(); |
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303 } |
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304 |
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305 static void |
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306 xor_p5_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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307 unsigned long *p3) |
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308 { |
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309 unsigned long lines = bytes >> 6; |
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310 |
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311 kernel_fpu_begin(); |
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312 |
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313 asm volatile( |
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314 " .align 32,0x90 ;\n" |
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315 " 1: ;\n" |
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316 " movq (%1), %%mm0 ;\n" |
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317 " movq 8(%1), %%mm1 ;\n" |
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318 " pxor (%2), %%mm0 ;\n" |
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319 " movq 16(%1), %%mm2 ;\n" |
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320 " pxor 8(%2), %%mm1 ;\n" |
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321 " pxor (%3), %%mm0 ;\n" |
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322 " pxor 16(%2), %%mm2 ;\n" |
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323 " movq %%mm0, (%1) ;\n" |
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324 " pxor 8(%3), %%mm1 ;\n" |
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325 " pxor 16(%3), %%mm2 ;\n" |
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326 " movq 24(%1), %%mm3 ;\n" |
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327 " movq %%mm1, 8(%1) ;\n" |
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328 " movq 32(%1), %%mm4 ;\n" |
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329 " movq 40(%1), %%mm5 ;\n" |
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330 " pxor 24(%2), %%mm3 ;\n" |
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331 " movq %%mm2, 16(%1) ;\n" |
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332 " pxor 32(%2), %%mm4 ;\n" |
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333 " pxor 24(%3), %%mm3 ;\n" |
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334 " pxor 40(%2), %%mm5 ;\n" |
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335 " movq %%mm3, 24(%1) ;\n" |
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336 " pxor 32(%3), %%mm4 ;\n" |
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337 " pxor 40(%3), %%mm5 ;\n" |
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338 " movq 48(%1), %%mm6 ;\n" |
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339 " movq %%mm4, 32(%1) ;\n" |
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340 " movq 56(%1), %%mm7 ;\n" |
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341 " pxor 48(%2), %%mm6 ;\n" |
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342 " movq %%mm5, 40(%1) ;\n" |
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343 " pxor 56(%2), %%mm7 ;\n" |
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344 " pxor 48(%3), %%mm6 ;\n" |
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345 " pxor 56(%3), %%mm7 ;\n" |
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346 " movq %%mm6, 48(%1) ;\n" |
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347 " movq %%mm7, 56(%1) ;\n" |
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348 |
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349 " addl $64, %1 ;\n" |
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350 " addl $64, %2 ;\n" |
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351 " addl $64, %3 ;\n" |
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352 " decl %0 ;\n" |
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353 " jnz 1b ;\n" |
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354 : "+r" (lines), |
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355 "+r" (p1), "+r" (p2), "+r" (p3) |
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356 : |
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357 : "memory" ); |
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358 |
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359 kernel_fpu_end(); |
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360 } |
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361 |
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362 static void |
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363 xor_p5_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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364 unsigned long *p3, unsigned long *p4) |
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365 { |
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366 unsigned long lines = bytes >> 6; |
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367 |
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368 kernel_fpu_begin(); |
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369 |
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370 asm volatile( |
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371 " .align 32,0x90 ;\n" |
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372 " 1: ;\n" |
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373 " movq (%1), %%mm0 ;\n" |
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374 " movq 8(%1), %%mm1 ;\n" |
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375 " pxor (%2), %%mm0 ;\n" |
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376 " movq 16(%1), %%mm2 ;\n" |
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377 " pxor 8(%2), %%mm1 ;\n" |
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378 " pxor (%3), %%mm0 ;\n" |
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379 " pxor 16(%2), %%mm2 ;\n" |
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380 " pxor 8(%3), %%mm1 ;\n" |
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381 " pxor (%4), %%mm0 ;\n" |
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382 " movq 24(%1), %%mm3 ;\n" |
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383 " pxor 16(%3), %%mm2 ;\n" |
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384 " pxor 8(%4), %%mm1 ;\n" |
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385 " movq %%mm0, (%1) ;\n" |
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386 " movq 32(%1), %%mm4 ;\n" |
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387 " pxor 24(%2), %%mm3 ;\n" |
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388 " pxor 16(%4), %%mm2 ;\n" |
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389 " movq %%mm1, 8(%1) ;\n" |
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390 " movq 40(%1), %%mm5 ;\n" |
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391 " pxor 32(%2), %%mm4 ;\n" |
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392 " pxor 24(%3), %%mm3 ;\n" |
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393 " movq %%mm2, 16(%1) ;\n" |
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394 " pxor 40(%2), %%mm5 ;\n" |
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395 " pxor 32(%3), %%mm4 ;\n" |
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396 " pxor 24(%4), %%mm3 ;\n" |
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397 " movq %%mm3, 24(%1) ;\n" |
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398 " movq 56(%1), %%mm7 ;\n" |
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399 " movq 48(%1), %%mm6 ;\n" |
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400 " pxor 40(%3), %%mm5 ;\n" |
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401 " pxor 32(%4), %%mm4 ;\n" |
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402 " pxor 48(%2), %%mm6 ;\n" |
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403 " movq %%mm4, 32(%1) ;\n" |
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404 " pxor 56(%2), %%mm7 ;\n" |
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405 " pxor 40(%4), %%mm5 ;\n" |
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406 " pxor 48(%3), %%mm6 ;\n" |
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407 " pxor 56(%3), %%mm7 ;\n" |
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408 " movq %%mm5, 40(%1) ;\n" |
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409 " pxor 48(%4), %%mm6 ;\n" |
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410 " pxor 56(%4), %%mm7 ;\n" |
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411 " movq %%mm6, 48(%1) ;\n" |
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412 " movq %%mm7, 56(%1) ;\n" |
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413 |
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414 " addl $64, %1 ;\n" |
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415 " addl $64, %2 ;\n" |
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416 " addl $64, %3 ;\n" |
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417 " addl $64, %4 ;\n" |
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418 " decl %0 ;\n" |
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419 " jnz 1b ;\n" |
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420 : "+r" (lines), |
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421 "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) |
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422 : |
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423 : "memory"); |
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424 |
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425 kernel_fpu_end(); |
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426 } |
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427 |
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428 static void |
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429 xor_p5_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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430 unsigned long *p3, unsigned long *p4, unsigned long *p5) |
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431 { |
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432 unsigned long lines = bytes >> 6; |
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433 |
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434 kernel_fpu_begin(); |
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435 |
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436 /* Make sure GCC forgets anything it knows about p4 or p5, |
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437 such that it won't pass to the asm volatile below a |
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438 register that is shared with any other variable. That's |
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439 because we modify p4 and p5 there, but we can't mark them |
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440 as read/write, otherwise we'd overflow the 10-asm-operands |
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441 limit of GCC < 3.1. */ |
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442 asm("" : "+r" (p4), "+r" (p5)); |
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443 |
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444 asm volatile( |
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445 " .align 32,0x90 ;\n" |
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446 " 1: ;\n" |
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447 " movq (%1), %%mm0 ;\n" |
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448 " movq 8(%1), %%mm1 ;\n" |
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449 " pxor (%2), %%mm0 ;\n" |
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450 " pxor 8(%2), %%mm1 ;\n" |
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451 " movq 16(%1), %%mm2 ;\n" |
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452 " pxor (%3), %%mm0 ;\n" |
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453 " pxor 8(%3), %%mm1 ;\n" |
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454 " pxor 16(%2), %%mm2 ;\n" |
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455 " pxor (%4), %%mm0 ;\n" |
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456 " pxor 8(%4), %%mm1 ;\n" |
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457 " pxor 16(%3), %%mm2 ;\n" |
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458 " movq 24(%1), %%mm3 ;\n" |
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459 " pxor (%5), %%mm0 ;\n" |
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460 " pxor 8(%5), %%mm1 ;\n" |
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461 " movq %%mm0, (%1) ;\n" |
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462 " pxor 16(%4), %%mm2 ;\n" |
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463 " pxor 24(%2), %%mm3 ;\n" |
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464 " movq %%mm1, 8(%1) ;\n" |
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465 " pxor 16(%5), %%mm2 ;\n" |
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466 " pxor 24(%3), %%mm3 ;\n" |
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467 " movq 32(%1), %%mm4 ;\n" |
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468 " movq %%mm2, 16(%1) ;\n" |
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469 " pxor 24(%4), %%mm3 ;\n" |
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470 " pxor 32(%2), %%mm4 ;\n" |
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471 " movq 40(%1), %%mm5 ;\n" |
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472 " pxor 24(%5), %%mm3 ;\n" |
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473 " pxor 32(%3), %%mm4 ;\n" |
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474 " pxor 40(%2), %%mm5 ;\n" |
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475 " movq %%mm3, 24(%1) ;\n" |
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476 " pxor 32(%4), %%mm4 ;\n" |
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477 " pxor 40(%3), %%mm5 ;\n" |
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478 " movq 48(%1), %%mm6 ;\n" |
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479 " movq 56(%1), %%mm7 ;\n" |
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480 " pxor 32(%5), %%mm4 ;\n" |
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481 " pxor 40(%4), %%mm5 ;\n" |
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482 " pxor 48(%2), %%mm6 ;\n" |
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483 " pxor 56(%2), %%mm7 ;\n" |
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484 " movq %%mm4, 32(%1) ;\n" |
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485 " pxor 48(%3), %%mm6 ;\n" |
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486 " pxor 56(%3), %%mm7 ;\n" |
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487 " pxor 40(%5), %%mm5 ;\n" |
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488 " pxor 48(%4), %%mm6 ;\n" |
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489 " pxor 56(%4), %%mm7 ;\n" |
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490 " movq %%mm5, 40(%1) ;\n" |
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491 " pxor 48(%5), %%mm6 ;\n" |
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492 " pxor 56(%5), %%mm7 ;\n" |
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493 " movq %%mm6, 48(%1) ;\n" |
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494 " movq %%mm7, 56(%1) ;\n" |
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495 |
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496 " addl $64, %1 ;\n" |
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497 " addl $64, %2 ;\n" |
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498 " addl $64, %3 ;\n" |
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499 " addl $64, %4 ;\n" |
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500 " addl $64, %5 ;\n" |
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501 " decl %0 ;\n" |
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502 " jnz 1b ;\n" |
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503 : "+r" (lines), |
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504 "+r" (p1), "+r" (p2), "+r" (p3) |
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505 : "r" (p4), "r" (p5) |
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506 : "memory"); |
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507 |
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508 /* p4 and p5 were modified, and now the variables are dead. |
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509 Clobber them just to be sure nobody does something stupid |
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510 like assuming they have some legal value. */ |
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511 asm("" : "=r" (p4), "=r" (p5)); |
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512 |
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513 kernel_fpu_end(); |
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514 } |
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515 |
|
516 static struct xor_block_template xor_block_pII_mmx = { |
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517 .name = "pII_mmx", |
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518 .do_2 = xor_pII_mmx_2, |
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519 .do_3 = xor_pII_mmx_3, |
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520 .do_4 = xor_pII_mmx_4, |
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521 .do_5 = xor_pII_mmx_5, |
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522 }; |
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523 |
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524 static struct xor_block_template xor_block_p5_mmx = { |
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525 .name = "p5_mmx", |
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526 .do_2 = xor_p5_mmx_2, |
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527 .do_3 = xor_p5_mmx_3, |
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528 .do_4 = xor_p5_mmx_4, |
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529 .do_5 = xor_p5_mmx_5, |
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530 }; |
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531 |
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532 /* |
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533 * Cache avoiding checksumming functions utilizing KNI instructions |
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534 * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo) |
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535 */ |
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536 |
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537 #define XMMS_SAVE \ |
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538 do { \ |
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539 preempt_disable(); \ |
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540 cr0 = read_cr0(); \ |
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541 clts(); \ |
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542 asm volatile( \ |
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543 "movups %%xmm0,(%0) ;\n\t" \ |
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544 "movups %%xmm1,0x10(%0) ;\n\t" \ |
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545 "movups %%xmm2,0x20(%0) ;\n\t" \ |
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546 "movups %%xmm3,0x30(%0) ;\n\t" \ |
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547 : \ |
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548 : "r" (xmm_save) \ |
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549 : "memory"); \ |
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550 } while (0) |
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551 |
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552 #define XMMS_RESTORE \ |
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553 do { \ |
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554 asm volatile( \ |
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555 "sfence ;\n\t" \ |
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556 "movups (%0),%%xmm0 ;\n\t" \ |
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557 "movups 0x10(%0),%%xmm1 ;\n\t" \ |
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558 "movups 0x20(%0),%%xmm2 ;\n\t" \ |
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559 "movups 0x30(%0),%%xmm3 ;\n\t" \ |
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560 : \ |
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561 : "r" (xmm_save) \ |
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562 : "memory"); \ |
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563 write_cr0(cr0); \ |
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564 preempt_enable(); \ |
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565 } while (0) |
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566 |
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567 #define ALIGN16 __attribute__((aligned(16))) |
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568 |
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569 #define OFFS(x) "16*("#x")" |
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570 #define PF_OFFS(x) "256+16*("#x")" |
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571 #define PF0(x) " prefetchnta "PF_OFFS(x)"(%1) ;\n" |
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572 #define LD(x, y) " movaps "OFFS(x)"(%1), %%xmm"#y" ;\n" |
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573 #define ST(x, y) " movaps %%xmm"#y", "OFFS(x)"(%1) ;\n" |
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574 #define PF1(x) " prefetchnta "PF_OFFS(x)"(%2) ;\n" |
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575 #define PF2(x) " prefetchnta "PF_OFFS(x)"(%3) ;\n" |
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576 #define PF3(x) " prefetchnta "PF_OFFS(x)"(%4) ;\n" |
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577 #define PF4(x) " prefetchnta "PF_OFFS(x)"(%5) ;\n" |
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578 #define PF5(x) " prefetchnta "PF_OFFS(x)"(%6) ;\n" |
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579 #define XO1(x, y) " xorps "OFFS(x)"(%2), %%xmm"#y" ;\n" |
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580 #define XO2(x, y) " xorps "OFFS(x)"(%3), %%xmm"#y" ;\n" |
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581 #define XO3(x, y) " xorps "OFFS(x)"(%4), %%xmm"#y" ;\n" |
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582 #define XO4(x, y) " xorps "OFFS(x)"(%5), %%xmm"#y" ;\n" |
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583 #define XO5(x, y) " xorps "OFFS(x)"(%6), %%xmm"#y" ;\n" |
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584 |
|
585 |
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586 static void |
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587 xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) |
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588 { |
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589 unsigned long lines = bytes >> 8; |
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590 char xmm_save[16*4] ALIGN16; |
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591 int cr0; |
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592 |
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593 XMMS_SAVE; |
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594 |
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595 asm volatile( |
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596 #undef BLOCK |
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597 #define BLOCK(i) \ |
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598 LD(i, 0) \ |
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599 LD(i + 1, 1) \ |
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600 PF1(i) \ |
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601 PF1(i + 2) \ |
|
602 LD(i + 2, 2) \ |
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603 LD(i + 3, 3) \ |
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604 PF0(i + 4) \ |
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605 PF0(i + 6) \ |
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606 XO1(i, 0) \ |
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607 XO1(i + 1, 1) \ |
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608 XO1(i + 2, 2) \ |
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609 XO1(i + 3, 3) \ |
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610 ST(i, 0) \ |
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611 ST(i + 1, 1) \ |
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612 ST(i + 2, 2) \ |
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613 ST(i + 3, 3) \ |
|
614 |
|
615 |
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616 PF0(0) |
|
617 PF0(2) |
|
618 |
|
619 " .align 32 ;\n" |
|
620 " 1: ;\n" |
|
621 |
|
622 BLOCK(0) |
|
623 BLOCK(4) |
|
624 BLOCK(8) |
|
625 BLOCK(12) |
|
626 |
|
627 " addl $256, %1 ;\n" |
|
628 " addl $256, %2 ;\n" |
|
629 " decl %0 ;\n" |
|
630 " jnz 1b ;\n" |
|
631 : "+r" (lines), |
|
632 "+r" (p1), "+r" (p2) |
|
633 : |
|
634 : "memory"); |
|
635 |
|
636 XMMS_RESTORE; |
|
637 } |
|
638 |
|
639 static void |
|
640 xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
|
641 unsigned long *p3) |
|
642 { |
|
643 unsigned long lines = bytes >> 8; |
|
644 char xmm_save[16*4] ALIGN16; |
|
645 int cr0; |
|
646 |
|
647 XMMS_SAVE; |
|
648 |
|
649 asm volatile( |
|
650 #undef BLOCK |
|
651 #define BLOCK(i) \ |
|
652 PF1(i) \ |
|
653 PF1(i + 2) \ |
|
654 LD(i,0) \ |
|
655 LD(i + 1, 1) \ |
|
656 LD(i + 2, 2) \ |
|
657 LD(i + 3, 3) \ |
|
658 PF2(i) \ |
|
659 PF2(i + 2) \ |
|
660 PF0(i + 4) \ |
|
661 PF0(i + 6) \ |
|
662 XO1(i,0) \ |
|
663 XO1(i + 1, 1) \ |
|
664 XO1(i + 2, 2) \ |
|
665 XO1(i + 3, 3) \ |
|
666 XO2(i,0) \ |
|
667 XO2(i + 1, 1) \ |
|
668 XO2(i + 2, 2) \ |
|
669 XO2(i + 3, 3) \ |
|
670 ST(i,0) \ |
|
671 ST(i + 1, 1) \ |
|
672 ST(i + 2, 2) \ |
|
673 ST(i + 3, 3) \ |
|
674 |
|
675 |
|
676 PF0(0) |
|
677 PF0(2) |
|
678 |
|
679 " .align 32 ;\n" |
|
680 " 1: ;\n" |
|
681 |
|
682 BLOCK(0) |
|
683 BLOCK(4) |
|
684 BLOCK(8) |
|
685 BLOCK(12) |
|
686 |
|
687 " addl $256, %1 ;\n" |
|
688 " addl $256, %2 ;\n" |
|
689 " addl $256, %3 ;\n" |
|
690 " decl %0 ;\n" |
|
691 " jnz 1b ;\n" |
|
692 : "+r" (lines), |
|
693 "+r" (p1), "+r"(p2), "+r"(p3) |
|
694 : |
|
695 : "memory" ); |
|
696 |
|
697 XMMS_RESTORE; |
|
698 } |
|
699 |
|
700 static void |
|
701 xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
|
702 unsigned long *p3, unsigned long *p4) |
|
703 { |
|
704 unsigned long lines = bytes >> 8; |
|
705 char xmm_save[16*4] ALIGN16; |
|
706 int cr0; |
|
707 |
|
708 XMMS_SAVE; |
|
709 |
|
710 asm volatile( |
|
711 #undef BLOCK |
|
712 #define BLOCK(i) \ |
|
713 PF1(i) \ |
|
714 PF1(i + 2) \ |
|
715 LD(i,0) \ |
|
716 LD(i + 1, 1) \ |
|
717 LD(i + 2, 2) \ |
|
718 LD(i + 3, 3) \ |
|
719 PF2(i) \ |
|
720 PF2(i + 2) \ |
|
721 XO1(i,0) \ |
|
722 XO1(i + 1, 1) \ |
|
723 XO1(i + 2, 2) \ |
|
724 XO1(i + 3, 3) \ |
|
725 PF3(i) \ |
|
726 PF3(i + 2) \ |
|
727 PF0(i + 4) \ |
|
728 PF0(i + 6) \ |
|
729 XO2(i,0) \ |
|
730 XO2(i + 1, 1) \ |
|
731 XO2(i + 2, 2) \ |
|
732 XO2(i + 3, 3) \ |
|
733 XO3(i,0) \ |
|
734 XO3(i + 1, 1) \ |
|
735 XO3(i + 2, 2) \ |
|
736 XO3(i + 3, 3) \ |
|
737 ST(i,0) \ |
|
738 ST(i + 1, 1) \ |
|
739 ST(i + 2, 2) \ |
|
740 ST(i + 3, 3) \ |
|
741 |
|
742 |
|
743 PF0(0) |
|
744 PF0(2) |
|
745 |
|
746 " .align 32 ;\n" |
|
747 " 1: ;\n" |
|
748 |
|
749 BLOCK(0) |
|
750 BLOCK(4) |
|
751 BLOCK(8) |
|
752 BLOCK(12) |
|
753 |
|
754 " addl $256, %1 ;\n" |
|
755 " addl $256, %2 ;\n" |
|
756 " addl $256, %3 ;\n" |
|
757 " addl $256, %4 ;\n" |
|
758 " decl %0 ;\n" |
|
759 " jnz 1b ;\n" |
|
760 : "+r" (lines), |
|
761 "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) |
|
762 : |
|
763 : "memory" ); |
|
764 |
|
765 XMMS_RESTORE; |
|
766 } |
|
767 |
|
768 static void |
|
769 xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
|
770 unsigned long *p3, unsigned long *p4, unsigned long *p5) |
|
771 { |
|
772 unsigned long lines = bytes >> 8; |
|
773 char xmm_save[16*4] ALIGN16; |
|
774 int cr0; |
|
775 |
|
776 XMMS_SAVE; |
|
777 |
|
778 /* Make sure GCC forgets anything it knows about p4 or p5, |
|
779 such that it won't pass to the asm volatile below a |
|
780 register that is shared with any other variable. That's |
|
781 because we modify p4 and p5 there, but we can't mark them |
|
782 as read/write, otherwise we'd overflow the 10-asm-operands |
|
783 limit of GCC < 3.1. */ |
|
784 asm("" : "+r" (p4), "+r" (p5)); |
|
785 |
|
786 asm volatile( |
|
787 #undef BLOCK |
|
788 #define BLOCK(i) \ |
|
789 PF1(i) \ |
|
790 PF1(i + 2) \ |
|
791 LD(i,0) \ |
|
792 LD(i + 1, 1) \ |
|
793 LD(i + 2, 2) \ |
|
794 LD(i + 3, 3) \ |
|
795 PF2(i) \ |
|
796 PF2(i + 2) \ |
|
797 XO1(i,0) \ |
|
798 XO1(i + 1, 1) \ |
|
799 XO1(i + 2, 2) \ |
|
800 XO1(i + 3, 3) \ |
|
801 PF3(i) \ |
|
802 PF3(i + 2) \ |
|
803 XO2(i,0) \ |
|
804 XO2(i + 1, 1) \ |
|
805 XO2(i + 2, 2) \ |
|
806 XO2(i + 3, 3) \ |
|
807 PF4(i) \ |
|
808 PF4(i + 2) \ |
|
809 PF0(i + 4) \ |
|
810 PF0(i + 6) \ |
|
811 XO3(i,0) \ |
|
812 XO3(i + 1, 1) \ |
|
813 XO3(i + 2, 2) \ |
|
814 XO3(i + 3, 3) \ |
|
815 XO4(i,0) \ |
|
816 XO4(i + 1, 1) \ |
|
817 XO4(i + 2, 2) \ |
|
818 XO4(i + 3, 3) \ |
|
819 ST(i,0) \ |
|
820 ST(i + 1, 1) \ |
|
821 ST(i + 2, 2) \ |
|
822 ST(i + 3, 3) \ |
|
823 |
|
824 |
|
825 PF0(0) |
|
826 PF0(2) |
|
827 |
|
828 " .align 32 ;\n" |
|
829 " 1: ;\n" |
|
830 |
|
831 BLOCK(0) |
|
832 BLOCK(4) |
|
833 BLOCK(8) |
|
834 BLOCK(12) |
|
835 |
|
836 " addl $256, %1 ;\n" |
|
837 " addl $256, %2 ;\n" |
|
838 " addl $256, %3 ;\n" |
|
839 " addl $256, %4 ;\n" |
|
840 " addl $256, %5 ;\n" |
|
841 " decl %0 ;\n" |
|
842 " jnz 1b ;\n" |
|
843 : "+r" (lines), |
|
844 "+r" (p1), "+r" (p2), "+r" (p3) |
|
845 : "r" (p4), "r" (p5) |
|
846 : "memory"); |
|
847 |
|
848 /* p4 and p5 were modified, and now the variables are dead. |
|
849 Clobber them just to be sure nobody does something stupid |
|
850 like assuming they have some legal value. */ |
|
851 asm("" : "=r" (p4), "=r" (p5)); |
|
852 |
|
853 XMMS_RESTORE; |
|
854 } |
|
855 |
|
856 static struct xor_block_template xor_block_pIII_sse = { |
|
857 .name = "pIII_sse", |
|
858 .do_2 = xor_sse_2, |
|
859 .do_3 = xor_sse_3, |
|
860 .do_4 = xor_sse_4, |
|
861 .do_5 = xor_sse_5, |
|
862 }; |
|
863 |
|
864 /* Also try the generic routines. */ |
|
865 #include <asm-generic/xor.h> |
|
866 |
|
867 #undef XOR_TRY_TEMPLATES |
|
868 #define XOR_TRY_TEMPLATES \ |
|
869 do { \ |
|
870 xor_speed(&xor_block_8regs); \ |
|
871 xor_speed(&xor_block_8regs_p); \ |
|
872 xor_speed(&xor_block_32regs); \ |
|
873 xor_speed(&xor_block_32regs_p); \ |
|
874 if (cpu_has_xmm) \ |
|
875 xor_speed(&xor_block_pIII_sse); \ |
|
876 if (cpu_has_mmx) { \ |
|
877 xor_speed(&xor_block_pII_mmx); \ |
|
878 xor_speed(&xor_block_p5_mmx); \ |
|
879 } \ |
|
880 } while (0) |
|
881 |
|
882 /* We force the use of the SSE xor block because it can write around L2. |
|
883 We may also be able to load into the L1 only depending on how the cpu |
|
884 deals with a load to a line that is being prefetched. */ |
|
885 #define XOR_SELECT_TEMPLATE(FASTEST) \ |
|
886 (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST) |
|
887 |
|
888 #endif /* _ASM_X86_XOR_32_H */ |