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1 #ifndef _ASM_X86_VISWS_COBALT_H |
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2 #define _ASM_X86_VISWS_COBALT_H |
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3 |
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4 #include <asm/fixmap.h> |
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5 |
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6 /* |
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7 * Cobalt SGI Visual Workstation system ASIC |
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8 */ |
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9 |
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10 #define CO_CPU_NUM_PHYS 0x1e00 |
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11 #define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2) |
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12 |
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13 #define CO_CPU_MAX 4 |
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14 |
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15 #define CO_CPU_PHYS 0xc2000000 |
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16 #define CO_APIC_PHYS 0xc4000000 |
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17 |
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18 /* see set_fixmap() and asm/fixmap.h */ |
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19 #define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU)) |
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20 #define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC)) |
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21 |
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22 /* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */ |
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23 #define CO_CPU_REV 0x08 |
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24 #define CO_CPU_CTRL 0x10 |
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25 #define CO_CPU_STAT 0x20 |
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26 #define CO_CPU_TIMEVAL 0x30 |
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27 |
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28 /* CO_CPU_CTRL bits */ |
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29 #define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */ |
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30 #define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */ |
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31 |
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32 /* CO_CPU_STATUS bits */ |
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33 #define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */ |
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34 |
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35 /* CO_CPU_TIMEVAL value */ |
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36 #define CO_TIME_HZ 100000000 /* Cobalt core rate */ |
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37 |
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38 /* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */ |
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39 #define CO_APIC_HI(n) (((n) * 0x10) + 4) |
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40 #define CO_APIC_LO(n) ((n) * 0x10) |
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41 #define CO_APIC_ID 0x0ffc |
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42 |
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43 /* CO_APIC_ID bits */ |
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44 #define CO_APIC_ENABLE 0x00000100 |
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45 |
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46 /* CO_APIC_LO bits */ |
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47 #define CO_APIC_MASK 0x00010000 /* 0 = enabled */ |
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48 #define CO_APIC_LEVEL 0x00008000 /* 0 = edge */ |
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49 |
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50 /* |
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51 * Where things are physically wired to Cobalt |
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52 * #defines with no board _<type>_<rev>_ are common to all (thus far) |
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53 */ |
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54 #define CO_APIC_IDE0 4 |
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55 #define CO_APIC_IDE1 2 /* Only on 320 */ |
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56 |
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57 #define CO_APIC_8259 12 /* serial, floppy, par-l-l */ |
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58 |
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59 /* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */ |
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60 #define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */ |
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61 #define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */ |
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62 |
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63 #define CO_APIC_PIIX4_USB 7 /* this one is weird */ |
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64 |
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65 /* Lithium PCI Bridge B -- "the one with PIIX4" */ |
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66 #define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */ |
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67 #define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */ |
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68 |
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69 #define CO_APIC_VIDOUT0 16 |
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70 #define CO_APIC_VIDOUT1 17 |
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71 #define CO_APIC_VIDIN0 18 |
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72 #define CO_APIC_VIDIN1 19 |
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73 |
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74 #define CO_APIC_LI_AUDIO 22 |
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75 |
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76 #define CO_APIC_AS 24 |
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77 #define CO_APIC_RE 25 |
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78 |
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79 #define CO_APIC_CPU 28 /* Timer and Cache interrupt */ |
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80 #define CO_APIC_NMI 29 |
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81 #define CO_APIC_LAST CO_APIC_NMI |
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82 |
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83 /* |
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84 * This is how irqs are assigned on the Visual Workstation. |
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85 * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU). |
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86 * All other devices (including PCI) go to Cobalt and are irq's 16 on up. |
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87 */ |
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88 #define CO_IRQ_APIC0 16 /* irq of apic entry 0 */ |
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89 #define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0) |
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90 #define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */ |
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91 #define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */ |
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92 #define CO_IRQ_IDE0 14 /* knowledge of... */ |
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93 #define CO_IRQ_IDE1 15 /* ... ide driver defaults! */ |
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94 #define CO_IRQ_8259 CO_IRQ(CO_APIC_8259) |
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95 |
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96 #ifdef CONFIG_X86_VISWS_APIC |
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97 static inline void co_cpu_write(unsigned long reg, unsigned long v) |
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98 { |
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99 *((volatile unsigned long *)(CO_CPU_VADDR+reg))=v; |
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100 } |
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101 |
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102 static inline unsigned long co_cpu_read(unsigned long reg) |
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103 { |
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104 return *((volatile unsigned long *)(CO_CPU_VADDR+reg)); |
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105 } |
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106 |
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107 static inline void co_apic_write(unsigned long reg, unsigned long v) |
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108 { |
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109 *((volatile unsigned long *)(CO_APIC_VADDR+reg))=v; |
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110 } |
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111 |
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112 static inline unsigned long co_apic_read(unsigned long reg) |
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113 { |
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114 return *((volatile unsigned long *)(CO_APIC_VADDR+reg)); |
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115 } |
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116 #endif |
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117 |
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118 extern char visws_board_type; |
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119 |
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120 #define VISWS_320 0 |
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121 #define VISWS_540 1 |
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122 |
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123 extern char visws_board_rev; |
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124 |
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125 #endif /* _ASM_X86_VISWS_COBALT_H */ |