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1 /* |
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2 * AMD Geode definitions |
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3 * Copyright (C) 2006, Advanced Micro Devices, Inc. |
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4 * |
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5 * This program is free software; you can redistribute it and/or |
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6 * modify it under the terms of version 2 of the GNU General Public License |
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7 * as published by the Free Software Foundation. |
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8 */ |
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9 |
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10 #ifndef _ASM_X86_GEODE_H |
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11 #define _ASM_X86_GEODE_H |
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12 |
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13 #include <asm/processor.h> |
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14 #include <linux/io.h> |
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15 |
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16 /* Generic southbridge functions */ |
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17 |
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18 #define GEODE_DEV_PMS 0 |
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19 #define GEODE_DEV_ACPI 1 |
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20 #define GEODE_DEV_GPIO 2 |
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21 #define GEODE_DEV_MFGPT 3 |
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22 |
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23 extern int geode_get_dev_base(unsigned int dev); |
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24 |
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25 /* Useful macros */ |
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26 #define geode_pms_base() geode_get_dev_base(GEODE_DEV_PMS) |
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27 #define geode_acpi_base() geode_get_dev_base(GEODE_DEV_ACPI) |
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28 #define geode_gpio_base() geode_get_dev_base(GEODE_DEV_GPIO) |
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29 #define geode_mfgpt_base() geode_get_dev_base(GEODE_DEV_MFGPT) |
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30 |
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31 /* MSRS */ |
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32 |
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33 #define MSR_GLIU_P2D_RO0 0x10000029 |
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34 |
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35 #define MSR_LX_GLD_MSR_CONFIG 0x48002001 |
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36 #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data |
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37 * sheet has the wrong value */ |
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38 #define MSR_GLCP_SYS_RSTPLL 0x4C000014 |
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39 #define MSR_GLCP_DOTPLL 0x4C000015 |
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40 |
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41 #define MSR_LBAR_SMB 0x5140000B |
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42 #define MSR_LBAR_GPIO 0x5140000C |
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43 #define MSR_LBAR_MFGPT 0x5140000D |
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44 #define MSR_LBAR_ACPI 0x5140000E |
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45 #define MSR_LBAR_PMS 0x5140000F |
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46 |
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47 #define MSR_DIVIL_SOFT_RESET 0x51400017 |
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48 |
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49 #define MSR_PIC_YSEL_LOW 0x51400020 |
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50 #define MSR_PIC_YSEL_HIGH 0x51400021 |
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51 #define MSR_PIC_ZSEL_LOW 0x51400022 |
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52 #define MSR_PIC_ZSEL_HIGH 0x51400023 |
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53 #define MSR_PIC_IRQM_LPC 0x51400025 |
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54 |
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55 #define MSR_MFGPT_IRQ 0x51400028 |
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56 #define MSR_MFGPT_NR 0x51400029 |
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57 #define MSR_MFGPT_SETUP 0x5140002B |
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58 |
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59 #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */ |
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60 |
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61 #define MSR_GX_GLD_MSR_CONFIG 0xC0002001 |
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62 #define MSR_GX_MSR_PADSEL 0xC0002011 |
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63 |
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64 /* Resource Sizes */ |
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65 |
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66 #define LBAR_GPIO_SIZE 0xFF |
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67 #define LBAR_MFGPT_SIZE 0x40 |
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68 #define LBAR_ACPI_SIZE 0x40 |
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69 #define LBAR_PMS_SIZE 0x80 |
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70 |
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71 /* ACPI registers (PMS block) */ |
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72 |
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73 /* |
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74 * PM1_EN is only valid when VSA is enabled for 16 bit reads. |
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75 * When VSA is not enabled, *always* read both PM1_STS and PM1_EN |
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76 * with a 32 bit read at offset 0x0 |
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77 */ |
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78 |
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79 #define PM1_STS 0x00 |
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80 #define PM1_EN 0x02 |
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81 #define PM1_CNT 0x08 |
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82 #define PM2_CNT 0x0C |
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83 #define PM_TMR 0x10 |
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84 #define PM_GPE0_STS 0x18 |
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85 #define PM_GPE0_EN 0x1C |
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86 |
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87 /* PMC registers (PMS block) */ |
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88 |
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89 #define PM_SSD 0x00 |
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90 #define PM_SCXA 0x04 |
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91 #define PM_SCYA 0x08 |
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92 #define PM_OUT_SLPCTL 0x0C |
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93 #define PM_SCLK 0x10 |
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94 #define PM_SED 0x1 |
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95 #define PM_SCXD 0x18 |
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96 #define PM_SCYD 0x1C |
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97 #define PM_IN_SLPCTL 0x20 |
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98 #define PM_WKD 0x30 |
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99 #define PM_WKXD 0x34 |
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100 #define PM_RD 0x38 |
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101 #define PM_WKXA 0x3C |
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102 #define PM_FSD 0x40 |
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103 #define PM_TSD 0x44 |
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104 #define PM_PSD 0x48 |
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105 #define PM_NWKD 0x4C |
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106 #define PM_AWKD 0x50 |
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107 #define PM_SSC 0x54 |
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108 |
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109 /* VSA2 magic values */ |
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110 |
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111 #define VSA_VRC_INDEX 0xAC1C |
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112 #define VSA_VRC_DATA 0xAC1E |
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113 #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */ |
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114 #define VSA_VR_SIGNATURE 0x0003 |
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115 #define VSA_VR_MEM_SIZE 0x0200 |
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116 #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */ |
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117 #define GSW_VSA_SIG 0x534d /* General Software signature */ |
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118 /* GPIO */ |
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119 |
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120 #define GPIO_OUTPUT_VAL 0x00 |
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121 #define GPIO_OUTPUT_ENABLE 0x04 |
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122 #define GPIO_OUTPUT_OPEN_DRAIN 0x08 |
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123 #define GPIO_OUTPUT_INVERT 0x0C |
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124 #define GPIO_OUTPUT_AUX1 0x10 |
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125 #define GPIO_OUTPUT_AUX2 0x14 |
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126 #define GPIO_PULL_UP 0x18 |
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127 #define GPIO_PULL_DOWN 0x1C |
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128 #define GPIO_INPUT_ENABLE 0x20 |
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129 #define GPIO_INPUT_INVERT 0x24 |
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130 #define GPIO_INPUT_FILTER 0x28 |
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131 #define GPIO_INPUT_EVENT_COUNT 0x2C |
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132 #define GPIO_READ_BACK 0x30 |
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133 #define GPIO_INPUT_AUX1 0x34 |
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134 #define GPIO_EVENTS_ENABLE 0x38 |
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135 #define GPIO_LOCK_ENABLE 0x3C |
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136 #define GPIO_POSITIVE_EDGE_EN 0x40 |
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137 #define GPIO_NEGATIVE_EDGE_EN 0x44 |
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138 #define GPIO_POSITIVE_EDGE_STS 0x48 |
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139 #define GPIO_NEGATIVE_EDGE_STS 0x4C |
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140 |
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141 #define GPIO_MAP_X 0xE0 |
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142 #define GPIO_MAP_Y 0xE4 |
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143 #define GPIO_MAP_Z 0xE8 |
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144 #define GPIO_MAP_W 0xEC |
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145 |
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146 static inline u32 geode_gpio(unsigned int nr) |
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147 { |
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148 BUG_ON(nr > 28); |
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149 return 1 << nr; |
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150 } |
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151 |
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152 extern void geode_gpio_set(u32, unsigned int); |
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153 extern void geode_gpio_clear(u32, unsigned int); |
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154 extern int geode_gpio_isset(u32, unsigned int); |
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155 extern void geode_gpio_setup_event(unsigned int, int, int); |
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156 extern void geode_gpio_set_irq(unsigned int, unsigned int); |
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157 |
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158 static inline void geode_gpio_event_irq(unsigned int gpio, int pair) |
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159 { |
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160 geode_gpio_setup_event(gpio, pair, 0); |
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161 } |
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162 |
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163 static inline void geode_gpio_event_pme(unsigned int gpio, int pair) |
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164 { |
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165 geode_gpio_setup_event(gpio, pair, 1); |
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166 } |
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167 |
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168 /* Specific geode tests */ |
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169 |
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170 static inline int is_geode_gx(void) |
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171 { |
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172 return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) && |
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173 (boot_cpu_data.x86 == 5) && |
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174 (boot_cpu_data.x86_model == 5)); |
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175 } |
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176 |
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177 static inline int is_geode_lx(void) |
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178 { |
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179 return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && |
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180 (boot_cpu_data.x86 == 5) && |
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181 (boot_cpu_data.x86_model == 10)); |
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182 } |
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183 |
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184 static inline int is_geode(void) |
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185 { |
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186 return (is_geode_gx() || is_geode_lx()); |
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187 } |
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188 |
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189 #ifdef CONFIG_MGEODE_LX |
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190 extern int geode_has_vsa2(void); |
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191 #else |
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192 static inline int geode_has_vsa2(void) |
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193 { |
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194 return 0; |
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195 } |
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196 #endif |
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197 |
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198 /* MFGPTs */ |
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199 |
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200 #define MFGPT_MAX_TIMERS 8 |
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201 #define MFGPT_TIMER_ANY (-1) |
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202 |
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203 #define MFGPT_DOMAIN_WORKING 1 |
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204 #define MFGPT_DOMAIN_STANDBY 2 |
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205 #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY) |
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206 |
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207 #define MFGPT_CMP1 0 |
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208 #define MFGPT_CMP2 1 |
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209 |
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210 #define MFGPT_EVENT_IRQ 0 |
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211 #define MFGPT_EVENT_NMI 1 |
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212 #define MFGPT_EVENT_RESET 3 |
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213 |
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214 #define MFGPT_REG_CMP1 0 |
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215 #define MFGPT_REG_CMP2 2 |
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216 #define MFGPT_REG_COUNTER 4 |
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217 #define MFGPT_REG_SETUP 6 |
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218 |
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219 #define MFGPT_SETUP_CNTEN (1 << 15) |
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220 #define MFGPT_SETUP_CMP2 (1 << 14) |
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221 #define MFGPT_SETUP_CMP1 (1 << 13) |
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222 #define MFGPT_SETUP_SETUP (1 << 12) |
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223 #define MFGPT_SETUP_STOPEN (1 << 11) |
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224 #define MFGPT_SETUP_EXTEN (1 << 10) |
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225 #define MFGPT_SETUP_REVEN (1 << 5) |
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226 #define MFGPT_SETUP_CLKSEL (1 << 4) |
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227 |
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228 static inline void geode_mfgpt_write(int timer, u16 reg, u16 value) |
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229 { |
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230 u32 base = geode_get_dev_base(GEODE_DEV_MFGPT); |
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231 outw(value, base + reg + (timer * 8)); |
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232 } |
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233 |
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234 static inline u16 geode_mfgpt_read(int timer, u16 reg) |
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235 { |
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236 u32 base = geode_get_dev_base(GEODE_DEV_MFGPT); |
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237 return inw(base + reg + (timer * 8)); |
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238 } |
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239 |
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240 extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable); |
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241 extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable); |
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242 extern int geode_mfgpt_alloc_timer(int timer, int domain); |
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243 |
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244 #define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1) |
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245 #define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0) |
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246 |
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247 #ifdef CONFIG_GEODE_MFGPT_TIMER |
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248 extern int __init mfgpt_timer_setup(void); |
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249 #else |
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250 static inline int mfgpt_timer_setup(void) { return 0; } |
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251 #endif |
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252 |
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253 #endif /* _ASM_X86_GEODE_H */ |