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1 #ifndef _ASM_X86_GART_H |
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2 #define _ASM_X86_GART_H |
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3 |
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4 #include <asm/e820.h> |
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5 |
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6 extern void set_up_gart_resume(u32, u32); |
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7 |
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8 extern int fallback_aper_order; |
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9 extern int fallback_aper_force; |
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10 extern int fix_aperture; |
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11 |
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12 /* PTE bits. */ |
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13 #define GPTE_VALID 1 |
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14 #define GPTE_COHERENT 2 |
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15 |
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16 /* Aperture control register bits. */ |
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17 #define GARTEN (1<<0) |
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18 #define DISGARTCPU (1<<4) |
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19 #define DISGARTIO (1<<5) |
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20 |
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21 /* GART cache control register bits. */ |
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22 #define INVGART (1<<0) |
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23 #define GARTPTEERR (1<<1) |
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24 |
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25 /* K8 On-cpu GART registers */ |
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26 #define AMD64_GARTAPERTURECTL 0x90 |
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27 #define AMD64_GARTAPERTUREBASE 0x94 |
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28 #define AMD64_GARTTABLEBASE 0x98 |
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29 #define AMD64_GARTCACHECTL 0x9c |
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30 #define AMD64_GARTEN (1<<0) |
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31 |
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32 extern int agp_amd64_init(void); |
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33 |
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34 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) |
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35 { |
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36 u32 tmp, ctl; |
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37 |
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38 /* address of the mappings table */ |
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39 addr >>= 12; |
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40 tmp = (u32) addr<<4; |
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41 tmp &= ~0xf; |
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42 pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); |
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43 |
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44 /* Enable GART translation for this hammer. */ |
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45 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
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46 ctl |= GARTEN; |
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47 ctl &= ~(DISGARTCPU | DISGARTIO); |
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48 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
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49 } |
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50 |
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51 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) |
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52 { |
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53 if (!aper_base) |
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54 return 0; |
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55 |
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56 if (aper_base + aper_size > 0x100000000ULL) { |
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57 printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n"); |
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58 return 0; |
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59 } |
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60 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { |
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61 printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n"); |
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62 return 0; |
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63 } |
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64 if (aper_size < min_size) { |
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65 printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n", |
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66 aper_size>>20, min_size>>20); |
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67 return 0; |
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68 } |
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69 |
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70 return 1; |
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71 } |
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72 |
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73 #endif /* _ASM_X86_GART_H */ |