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1 #ifndef _ASM_X86_APICDEF_H |
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2 #define _ASM_X86_APICDEF_H |
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3 |
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4 /* |
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5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) |
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6 * |
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7 * Alan Cox <Alan.Cox@linux.org>, 1995. |
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8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 |
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9 */ |
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10 |
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11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 |
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12 |
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13 #define APIC_ID 0x20 |
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14 |
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15 #define APIC_LVR 0x30 |
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16 #define APIC_LVR_MASK 0xFF00FF |
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17 #define GET_APIC_VERSION(x) ((x) & 0xFFu) |
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18 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) |
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19 #ifdef CONFIG_X86_32 |
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20 # define APIC_INTEGRATED(x) ((x) & 0xF0u) |
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21 #else |
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22 # define APIC_INTEGRATED(x) (1) |
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23 #endif |
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24 #define APIC_XAPIC(x) ((x) >= 0x14) |
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25 #define APIC_TASKPRI 0x80 |
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26 #define APIC_TPRI_MASK 0xFFu |
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27 #define APIC_ARBPRI 0x90 |
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28 #define APIC_ARBPRI_MASK 0xFFu |
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29 #define APIC_PROCPRI 0xA0 |
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30 #define APIC_EOI 0xB0 |
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31 #define APIC_EIO_ACK 0x0 |
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32 #define APIC_RRR 0xC0 |
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33 #define APIC_LDR 0xD0 |
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34 #define APIC_LDR_MASK (0xFFu << 24) |
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35 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) |
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36 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) |
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37 #define APIC_ALL_CPUS 0xFFu |
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38 #define APIC_DFR 0xE0 |
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39 #define APIC_DFR_CLUSTER 0x0FFFFFFFul |
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40 #define APIC_DFR_FLAT 0xFFFFFFFFul |
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41 #define APIC_SPIV 0xF0 |
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42 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) |
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43 #define APIC_SPIV_APIC_ENABLED (1 << 8) |
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44 #define APIC_ISR 0x100 |
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45 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ |
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46 #define APIC_TMR 0x180 |
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47 #define APIC_IRR 0x200 |
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48 #define APIC_ESR 0x280 |
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49 #define APIC_ESR_SEND_CS 0x00001 |
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50 #define APIC_ESR_RECV_CS 0x00002 |
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51 #define APIC_ESR_SEND_ACC 0x00004 |
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52 #define APIC_ESR_RECV_ACC 0x00008 |
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53 #define APIC_ESR_SENDILL 0x00020 |
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54 #define APIC_ESR_RECVILL 0x00040 |
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55 #define APIC_ESR_ILLREGA 0x00080 |
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56 #define APIC_ICR 0x300 |
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57 #define APIC_DEST_SELF 0x40000 |
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58 #define APIC_DEST_ALLINC 0x80000 |
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59 #define APIC_DEST_ALLBUT 0xC0000 |
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60 #define APIC_ICR_RR_MASK 0x30000 |
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61 #define APIC_ICR_RR_INVALID 0x00000 |
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62 #define APIC_ICR_RR_INPROG 0x10000 |
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63 #define APIC_ICR_RR_VALID 0x20000 |
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64 #define APIC_INT_LEVELTRIG 0x08000 |
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65 #define APIC_INT_ASSERT 0x04000 |
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66 #define APIC_ICR_BUSY 0x01000 |
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67 #define APIC_DEST_LOGICAL 0x00800 |
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68 #define APIC_DEST_PHYSICAL 0x00000 |
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69 #define APIC_DM_FIXED 0x00000 |
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70 #define APIC_DM_LOWEST 0x00100 |
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71 #define APIC_DM_SMI 0x00200 |
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72 #define APIC_DM_REMRD 0x00300 |
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73 #define APIC_DM_NMI 0x00400 |
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74 #define APIC_DM_INIT 0x00500 |
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75 #define APIC_DM_STARTUP 0x00600 |
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76 #define APIC_DM_EXTINT 0x00700 |
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77 #define APIC_VECTOR_MASK 0x000FF |
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78 #define APIC_ICR2 0x310 |
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79 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) |
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80 #define SET_APIC_DEST_FIELD(x) ((x) << 24) |
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81 #define APIC_LVTT 0x320 |
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82 #define APIC_LVTTHMR 0x330 |
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83 #define APIC_LVTPC 0x340 |
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84 #define APIC_LVT0 0x350 |
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85 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) |
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86 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) |
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87 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) |
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88 #define APIC_TIMER_BASE_CLKIN 0x0 |
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89 #define APIC_TIMER_BASE_TMBASE 0x1 |
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90 #define APIC_TIMER_BASE_DIV 0x2 |
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91 #define APIC_LVT_TIMER_PERIODIC (1 << 17) |
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92 #define APIC_LVT_MASKED (1 << 16) |
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93 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) |
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94 #define APIC_LVT_REMOTE_IRR (1 << 14) |
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95 #define APIC_INPUT_POLARITY (1 << 13) |
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96 #define APIC_SEND_PENDING (1 << 12) |
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97 #define APIC_MODE_MASK 0x700 |
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98 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) |
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99 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) |
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100 #define APIC_MODE_FIXED 0x0 |
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101 #define APIC_MODE_NMI 0x4 |
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102 #define APIC_MODE_EXTINT 0x7 |
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103 #define APIC_LVT1 0x360 |
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104 #define APIC_LVTERR 0x370 |
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105 #define APIC_TMICT 0x380 |
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106 #define APIC_TMCCT 0x390 |
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107 #define APIC_TDCR 0x3E0 |
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108 #define APIC_SELF_IPI 0x3F0 |
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109 #define APIC_TDR_DIV_TMBASE (1 << 2) |
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110 #define APIC_TDR_DIV_1 0xB |
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111 #define APIC_TDR_DIV_2 0x0 |
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112 #define APIC_TDR_DIV_4 0x1 |
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113 #define APIC_TDR_DIV_8 0x2 |
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114 #define APIC_TDR_DIV_16 0x3 |
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115 #define APIC_TDR_DIV_32 0x8 |
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116 #define APIC_TDR_DIV_64 0x9 |
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117 #define APIC_TDR_DIV_128 0xA |
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118 #define APIC_EILVT0 0x500 |
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119 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ |
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120 #define APIC_EILVT_NR_AMD_10H 4 |
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121 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) |
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122 #define APIC_EILVT_MSG_FIX 0x0 |
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123 #define APIC_EILVT_MSG_SMI 0x2 |
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124 #define APIC_EILVT_MSG_NMI 0x4 |
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125 #define APIC_EILVT_MSG_EXT 0x7 |
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126 #define APIC_EILVT_MASKED (1 << 16) |
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127 #define APIC_EILVT1 0x510 |
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128 #define APIC_EILVT2 0x520 |
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129 #define APIC_EILVT3 0x530 |
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130 |
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131 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
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132 #define APIC_BASE_MSR 0x800 |
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133 #define X2APIC_ENABLE (1UL << 10) |
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134 |
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135 #ifdef CONFIG_X86_32 |
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136 # define MAX_IO_APICS 64 |
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137 #else |
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138 # define MAX_IO_APICS 128 |
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139 # define MAX_LOCAL_APIC 32768 |
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140 #endif |
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141 |
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142 /* |
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143 * All x86-64 systems are xAPIC compatible. |
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144 * In the following, "apicid" is a physical APIC ID. |
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145 */ |
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146 #define XAPIC_DEST_CPUS_SHIFT 4 |
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147 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) |
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148 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) |
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149 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) |
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150 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) |
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151 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) |
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152 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) |
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153 |
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154 /* |
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155 * the local APIC register structure, memory mapped. Not terribly well |
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156 * tested, but we might eventually use this one in the future - the |
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157 * problem why we cannot use it right now is the P5 APIC, it has an |
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158 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... |
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159 */ |
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160 #define u32 unsigned int |
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161 |
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162 struct local_apic { |
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163 |
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164 /*000*/ struct { u32 __reserved[4]; } __reserved_01; |
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165 |
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166 /*010*/ struct { u32 __reserved[4]; } __reserved_02; |
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167 |
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168 /*020*/ struct { /* APIC ID Register */ |
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169 u32 __reserved_1 : 24, |
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170 phys_apic_id : 4, |
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171 __reserved_2 : 4; |
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172 u32 __reserved[3]; |
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173 } id; |
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174 |
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175 /*030*/ const |
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176 struct { /* APIC Version Register */ |
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177 u32 version : 8, |
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178 __reserved_1 : 8, |
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179 max_lvt : 8, |
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180 __reserved_2 : 8; |
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181 u32 __reserved[3]; |
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182 } version; |
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183 |
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184 /*040*/ struct { u32 __reserved[4]; } __reserved_03; |
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185 |
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186 /*050*/ struct { u32 __reserved[4]; } __reserved_04; |
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187 |
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188 /*060*/ struct { u32 __reserved[4]; } __reserved_05; |
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189 |
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190 /*070*/ struct { u32 __reserved[4]; } __reserved_06; |
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191 |
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192 /*080*/ struct { /* Task Priority Register */ |
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193 u32 priority : 8, |
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194 __reserved_1 : 24; |
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195 u32 __reserved_2[3]; |
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196 } tpr; |
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197 |
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198 /*090*/ const |
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199 struct { /* Arbitration Priority Register */ |
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200 u32 priority : 8, |
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201 __reserved_1 : 24; |
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202 u32 __reserved_2[3]; |
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203 } apr; |
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204 |
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205 /*0A0*/ const |
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206 struct { /* Processor Priority Register */ |
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207 u32 priority : 8, |
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208 __reserved_1 : 24; |
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209 u32 __reserved_2[3]; |
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210 } ppr; |
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211 |
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212 /*0B0*/ struct { /* End Of Interrupt Register */ |
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213 u32 eoi; |
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214 u32 __reserved[3]; |
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215 } eoi; |
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216 |
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217 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; |
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218 |
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219 /*0D0*/ struct { /* Logical Destination Register */ |
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220 u32 __reserved_1 : 24, |
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221 logical_dest : 8; |
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222 u32 __reserved_2[3]; |
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223 } ldr; |
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224 |
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225 /*0E0*/ struct { /* Destination Format Register */ |
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226 u32 __reserved_1 : 28, |
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227 model : 4; |
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228 u32 __reserved_2[3]; |
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229 } dfr; |
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230 |
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231 /*0F0*/ struct { /* Spurious Interrupt Vector Register */ |
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232 u32 spurious_vector : 8, |
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233 apic_enabled : 1, |
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234 focus_cpu : 1, |
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235 __reserved_2 : 22; |
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236 u32 __reserved_3[3]; |
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237 } svr; |
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238 |
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239 /*100*/ struct { /* In Service Register */ |
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240 /*170*/ u32 bitfield; |
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241 u32 __reserved[3]; |
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242 } isr [8]; |
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243 |
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244 /*180*/ struct { /* Trigger Mode Register */ |
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245 /*1F0*/ u32 bitfield; |
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246 u32 __reserved[3]; |
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247 } tmr [8]; |
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248 |
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249 /*200*/ struct { /* Interrupt Request Register */ |
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250 /*270*/ u32 bitfield; |
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251 u32 __reserved[3]; |
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252 } irr [8]; |
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253 |
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254 /*280*/ union { /* Error Status Register */ |
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255 struct { |
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256 u32 send_cs_error : 1, |
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257 receive_cs_error : 1, |
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258 send_accept_error : 1, |
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259 receive_accept_error : 1, |
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260 __reserved_1 : 1, |
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261 send_illegal_vector : 1, |
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262 receive_illegal_vector : 1, |
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263 illegal_register_address : 1, |
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264 __reserved_2 : 24; |
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265 u32 __reserved_3[3]; |
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266 } error_bits; |
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267 struct { |
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268 u32 errors; |
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269 u32 __reserved_3[3]; |
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270 } all_errors; |
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271 } esr; |
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272 |
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273 /*290*/ struct { u32 __reserved[4]; } __reserved_08; |
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274 |
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275 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; |
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276 |
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277 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; |
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278 |
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279 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; |
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280 |
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281 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; |
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282 |
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283 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; |
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284 |
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285 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; |
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286 |
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287 /*300*/ struct { /* Interrupt Command Register 1 */ |
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288 u32 vector : 8, |
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289 delivery_mode : 3, |
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290 destination_mode : 1, |
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291 delivery_status : 1, |
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292 __reserved_1 : 1, |
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293 level : 1, |
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294 trigger : 1, |
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295 __reserved_2 : 2, |
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296 shorthand : 2, |
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297 __reserved_3 : 12; |
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298 u32 __reserved_4[3]; |
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299 } icr1; |
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300 |
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301 /*310*/ struct { /* Interrupt Command Register 2 */ |
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302 union { |
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303 u32 __reserved_1 : 24, |
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304 phys_dest : 4, |
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305 __reserved_2 : 4; |
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306 u32 __reserved_3 : 24, |
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307 logical_dest : 8; |
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308 } dest; |
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309 u32 __reserved_4[3]; |
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310 } icr2; |
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311 |
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312 /*320*/ struct { /* LVT - Timer */ |
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313 u32 vector : 8, |
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314 __reserved_1 : 4, |
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315 delivery_status : 1, |
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316 __reserved_2 : 3, |
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317 mask : 1, |
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318 timer_mode : 1, |
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319 __reserved_3 : 14; |
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320 u32 __reserved_4[3]; |
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321 } lvt_timer; |
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322 |
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323 /*330*/ struct { /* LVT - Thermal Sensor */ |
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324 u32 vector : 8, |
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325 delivery_mode : 3, |
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326 __reserved_1 : 1, |
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327 delivery_status : 1, |
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328 __reserved_2 : 3, |
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329 mask : 1, |
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330 __reserved_3 : 15; |
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331 u32 __reserved_4[3]; |
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332 } lvt_thermal; |
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333 |
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334 /*340*/ struct { /* LVT - Performance Counter */ |
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335 u32 vector : 8, |
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336 delivery_mode : 3, |
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337 __reserved_1 : 1, |
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338 delivery_status : 1, |
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339 __reserved_2 : 3, |
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340 mask : 1, |
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341 __reserved_3 : 15; |
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342 u32 __reserved_4[3]; |
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343 } lvt_pc; |
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344 |
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345 /*350*/ struct { /* LVT - LINT0 */ |
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346 u32 vector : 8, |
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347 delivery_mode : 3, |
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348 __reserved_1 : 1, |
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349 delivery_status : 1, |
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350 polarity : 1, |
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351 remote_irr : 1, |
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352 trigger : 1, |
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353 mask : 1, |
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354 __reserved_2 : 15; |
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355 u32 __reserved_3[3]; |
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356 } lvt_lint0; |
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357 |
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358 /*360*/ struct { /* LVT - LINT1 */ |
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359 u32 vector : 8, |
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360 delivery_mode : 3, |
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361 __reserved_1 : 1, |
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362 delivery_status : 1, |
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363 polarity : 1, |
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364 remote_irr : 1, |
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365 trigger : 1, |
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366 mask : 1, |
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367 __reserved_2 : 15; |
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368 u32 __reserved_3[3]; |
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369 } lvt_lint1; |
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370 |
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371 /*370*/ struct { /* LVT - Error */ |
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372 u32 vector : 8, |
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373 __reserved_1 : 4, |
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374 delivery_status : 1, |
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375 __reserved_2 : 3, |
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376 mask : 1, |
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377 __reserved_3 : 15; |
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378 u32 __reserved_4[3]; |
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379 } lvt_error; |
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380 |
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381 /*380*/ struct { /* Timer Initial Count Register */ |
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382 u32 initial_count; |
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383 u32 __reserved_2[3]; |
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384 } timer_icr; |
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385 |
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386 /*390*/ const |
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387 struct { /* Timer Current Count Register */ |
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388 u32 curr_count; |
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389 u32 __reserved_2[3]; |
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390 } timer_ccr; |
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391 |
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392 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; |
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393 |
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394 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; |
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395 |
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396 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; |
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397 |
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398 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; |
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399 |
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400 /*3E0*/ struct { /* Timer Divide Configuration Register */ |
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401 u32 divisor : 4, |
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402 __reserved_1 : 28; |
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403 u32 __reserved_2[3]; |
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404 } timer_dcr; |
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405 |
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406 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; |
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407 |
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408 } __attribute__ ((packed)); |
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409 |
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410 #undef u32 |
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411 |
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412 #ifdef CONFIG_X86_32 |
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413 #define BAD_APICID 0xFFu |
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414 #else |
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415 #define BAD_APICID 0xFFFFu |
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416 #endif |
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417 #endif /* _ASM_X86_APICDEF_H */ |